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ramtron international corporation ? http://www.ramtron.com 1850 ramtron drive colorado springs ? mcu customer service: 1 - 800 - 943 - 4625, 1 - 514 - 871 - 2447, ext. 20 8 colorado , usa, 8092 1 ? 1 - 800 - 545 - fram, 1 - 719 - 481 - 7000 vmx1c1020 datasheet rev 2.12 versa mix 8051 mixed - signal mcu overview the vmx51c1020 is a fully integrated mixed - signal microcontroller that provides a ?one - chip solution? for a broad range of signal conditioning, data acquisition, processing, and control applications. the vmx51c1020 is based on a powerful single - cycle, risc - based, 8051 microprocessor with an enhanced mult/accu unit that can be used to perform complex mathematical operations. on - chip analog peripherals such as: an a/d converter, pwm outputs (that can be used as d/a co nverters), a voltage reference, a programmable current source, an uncommitted operational amplifier, digital potentiometers and an analog switch makes the vmx51c1020 ideal for analog data acquisition applications. the inclusion of a full set of digital i nterfaces such as an enhanced fully configurable spi, an i 2 c interface, uarts and a j1708/rs - 485/rs - 422 compatible differential transceiver , enables total system integration. applications o automotive applications o industrial controls / instrumentation o consum er products o intelligent sensors o medical devices f igure 1: vmx51c1020 b lock d iagram feature set o 8051 compatible risc performance processor. o integrated debugger o 56kb flash program memory o 1280 bytes of ram o mult/accu unit including a barrel shifter o provides dsp capabilities o 2 uart serial ports o 2 baud rate generators for uarts o differential transceiver connected to uart1 j1708/rs - 485/rs - 422 compatible. o enhanced spi interface (master/slave) o fully configurable o controls up to 4 slave de vices o i2c interface o 28 general purpose i/os o 2 external interrupt inputs o interrupt on port 1 pin change o 3, 16 - bit timers/counters o 4 compare & capture units with 3 capture inputs o 4 pwm outputs, 8 - bit / 16 - bit resolution o 4 ext. + 3 int. channel 12 - bit a/d c onverter o conversion rate up to 10khz o 0 - 2.7 volt input range continuous / one - shot operation o single or 4 - channel automatic sequential conversions o on - chip voltage reference o programmable current source o operational amplifier o 2 digital potentiometers o 1 digit ally controlled switch o power saving features + clock control o power - on reset with brown - out detect o watchdog timer f igure 2: vmx51c1020 qfp - 64 p ackage p inout 4 8 49 32 33 64 16 17 1 p 1 . 3 pwm 3 p 1 . 2 pwm 2 int 1 ccu 2 p 2 . 0 ? cs 3 - dgnd p 2 . 2 ? cs 1 - p 2 . 1 ? cs 2 - p 2 . 4 ? ss - p 2 . 3 ? cs 0 - p 2 . 6 ? sdo p 2 . 5 ? sck vdd p 2 . 7 ? sdi p 1 . 5 p 1 . 4 o p i n + o p i n - p o t 1 b p o t 1 a s w 1 b s w 1 a r x 1 d - t x 1 d - r x 1 d + t x 1 d + p 0 . 2 ? t x 1 p 0 . 3 ? r x 1 p 0 . 0 ? t 2 i n p 0 . 1 ? t 2 e x p 1 . 1 ? p w m 1 p 1 . 0 ? p w m 0 agnd opout adci 0 xtvref adci 2 adci 1 vdda adci 3 pot 2 a pot 2 b isrcout ? ta isrcin pm res - agnd int 0 p 1 . 7 p 1 . 6 o s c 0 o s c 1 p 3 . 1 ? r x 0 p 3 . 0 ? t x 0 v d d p 3 . 2 ? t 0 i n p 3 . 4 ? c c u 1 p 3 . 3 ? c c u 0 v p p p 3 . 5 ? t 1 i n n c p 3 . 6 ? s d a p 3 . 7 - s c l n c vmx 51 c 1020 8051 processor single cycle in - circuit debugging through uart 0 2 uarts serial ports 56 k b program flash ( in - circuit programmable ) 1280 bytes ram ( 256 x 8 & 1 kx 8 ) 2 interrupt inputs 28 i / os , interrupt on port 1 change 3 timers , 2 baud rate generators 4 ccu units [ mult / accu ] unit with barrel shifter spi interface i 2 c bus interface power on reset circuit + watchdog timer clock control unit j 1708 / rs 485 / rs 422 compatible transceiver xtal + i 4 pwm d / as 4 pwm d / as 4 pwm d / as 4 pwm outputs 8 / 16 bit resolution ( can be used as d / as ) 2 digital potentiometers 1 digitally controlled switch operational amplifier programmable current source 12 - bit a / d converter isrcin , isrcout , opout are internally connected to a / d input multiplexer a / d i n p u t m u x . band gap reference pga xtvref input
vmx51c1020 __________________________________________________________________________ _______________________________ www.ramtron.com page 2 of 80 vmx51c1020 pins description table 1: pin out desc ription pin name function 1 opin - inverting input of the operational amplifier 2 opin+ non - inverting input of the operational amplifier 3 pot1a digitally controlled potentiometer 1a 4 pot1b digitally controlled potentiometer 1b 5 sw1a digitally co ntrolled switch 1a 6 sw1b digitally controlled switch 1b 7 tx1d - rs - 485/rs422 compatible differential transmitter, negative side 8 rx1d - rs - 485/rs422 compatible differential receiver negative side 9 tx1d+ rs - 485/rs422 compatible differential transmitt er, positive side 10 rx1d+ rs - 485/rs422 compatible differential receiver positive side 11 p0.3 - rx1 i/o - asynchronous uart1 receiver input 12 p0.2 - tx1 i/o - asynchronous uart1 transmitter output 13 p0.1 - t2ex i/o - timer/counter 2 input 14 p0.0 - t2in i/ o - timer/counter 2 input 15 p1.0 - pwm0 i/o - pulse width modulator output 0 16 p1.1 - pwm1 i/o - pulse width modulator output 1 17 p1.2 - pwm2 i/o - pulse width modulator output 2 18 p1.3 - pwm3 i/o - pulse width modulator output 3 19 ccu2 capture and c ompare unit 2 input 20 int1 interrupt input 1 21 dgnd digital ground 22 p2.0 - cs3 - i/o - spi chip enable output (master mode) 23 p2.1 - cs2 - i/o - spi chip enable output (master mode) 24 p2.2 - cs1 - i/o - spi chip enable output (master mode) 25 p2.3 - cs0 - i/o - spi chip enable output (master mode) 26 p2.4 - ss - i/o - spi chip enable output (slave mode) 27 p2.5 - sck i/o - spi clock (input in slave mode) 28 p2.6 - sdo i/o - spi data output bus 29 p2.7 - sdi i/o - spi data input bus 30 vdd digital supply 31 p1. 4 i/o 32 p1.5 i/o 33 p1.6 i/o 34 p1.7 i/o 35 osc1 oscillator crystal output 36 osc0 oscillator crystal input/external clock source input 37 p3.0 - tx0 i/o - asynchronous uart0 transmitter output 38 p3.1 - rx0 i/o - asynchronous uart0 receiver input pin name function 3 9 p3.2 - t0in i/o - timer/counter 0 input 40 vdd 5v digital 41 p3.3 - ccu0 i/o - capture and compare unit 0 input 42 p3.4 - ccu1 i/o - capture and compare unit 1 input 43 p3.5 - t1in i/o - timer/counter 1 input 44 vpp flash programming voltage input 45 p3.6 - sda i/o - i2c / prog. interface bi - directional data bus 46 nc not connected, leave floating 47 nc not connected 48 p3.7 - scl i/o - i2c / prog. interface clock 49 agnd analog ground 50 int0 external interrupt input (negative level or edge triggered) 5 1 pm mode control input 52 res - hardware reset input (active low) 53 isrcout - ta programmable current source analog output 54 isrcin programmable current source input 55 pot2a digitally controlled potentiometer 2a 56 pot2b digitally controlled potenti ometer 2b 57 vdda analog supply 58 adci3 analog to digital converter ext. input 3 59 adci2 analog to digital converter ext. input 2 60 adci1 analog to digital converter ext. input 1 61 adci0 analog to digital converter ext. input 0 62 xtvref externa l reference voltage input 63 agnd analog ground 64 opout output of the operational amplifier f igure 3: vmx51c1020 pinout 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 49 32 33 p 1 . 3 pwm 3 p 1 . 2 pwm 2 int 1 ccu 2 p 2 . 0 ? cs 3 - dgnd p 2 . 2 ? cs 1 - p 2 . 1 ? cs 2 - p 2 . 4 ? ss - p 2 . 3 ? cs 0 - p 2 . 6 ? sdo p 2 . 5 ? sck vdd p 2 . 7 ? sdi p 1 . 5 p 1 . 4 o p i n + o p i n - p o t 1 b p o t 1 a s w 1 b s w 1 a r x 1 d - t x 1 d - r x 1 d + t x 1 d + p 0 . 2 ? t x 1 p 0 . 3 ? r x 1 p 0 . 0 ? t 2 i n p 0 . 1 ? t 2 e x p 1 . 1 ? p w m 1 p 1 . 0 ? p w m 0 agnd opout adci 0 xtvref adci 2 adci 1 vdda adci 3 pot 2 a pot 2 b isrcout ? ta isrcin pm res - agnd int 0 p 1 . 7 p 1 . 6 o s c 0 o s c 1 p 3 . 1 ? r x 0 p 3 . 0 ? t x 0 v d d p 3 . 2 ? t 0 i n p 3 . 4 ? c c u 1 p 3 . 3 ? c c u 0 v p p p 3 . 5 ? t 1 i n n c p 3 . 6 ? s d a p 3 . 7 - s c l n c 18 19 20 21 22 23 24 25 26 27 28 29 30 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 vmx 51 c 1020
vmx51c1020 _________________________________________________________________________________________________________ www.ramtron.com page 3 of 80 vmx51c1020 block diagram f igure 4: vmx51c1020 b lock d iagram 8051 processor single cycle in - circuit debugging through uart 0 2 uarts serial ports 56 k b program flash ( in - circuit programmable ) 1280 bytes ram ( 256 x 8 & 1 kx 8 ) 2 interrupt inputs 28 i / os , interrupt on port 1 change 3 timers , 2 baud . rate generators 4 ccu units [ mult / accu ] unit with barrel shifter spi interface i 2 c bus interface power on reset circuit + watchdog timer clock control unit j 1708 / rs 485 / rs 422 compatible transceiver xtal + i 4 pwm d / as 4 pwm d / as 4 pwm d / as 4 pwm outputs 8 / 16 bit resolution ( can be used as d / as ) 2 digital potentiometers 1 digitally controlled switch operational amplifier programmable current source 12 - bit a / d converter isrcin , isrcout , opout are internally connected to a / d input multiplexer a / d i n p u t m u x . band gap reference pga xtvref input
vmx51c1020 _________________________________________________________________________________________________________ www.ramtron.com page 4 of 80 absolute maximum ratings v dd to dgnd ? 0.3v, +6v digital output voltage to dgnd ? 0.3v, v dd +0.3v v dda to dgnd - 0.3v, +6v v pp to dgnd +13v agnd to dgnd ? 0.3v, +0.3v power dissipation v dd to v dda - 0.3v, +0.3 v to +70c 1000mw adci (0 - 3) to agnd - 0.3v, v dda +0.3v xtvref to agnd - 0.3v, v dda +0.3v operating temperature range 0 to +70c digital input voltage to dgnd - 0.3v, v dd +0.3v storage temperature range ? 65c to +110c rs422/485 minimum and maxi mum voltages - 2v, +7v lead temperature (soldering, 10sec) +300c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or a ny other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t able 2: e lectrical c haracteristics parameter symbol conditions min typ max units general characteristics (v dd = +5v, v dda = +5v, t a = +25c, 14.75mhz input clock, unless otherwise noted.) v dd 4.75 5.0 5.5 v power supply voltage v dda 4.5 5.0 5.5 v i dd (14.75mhz) 5 45* i dd (1mhz) 0.6 6* ma *depends on clock speed and peripheral use and load power supply current i dda 0.1 5* flash programming voltage v pp 11 13 v digital inputs minimum high - level input v ih v dd = +5v 2.0 v ma ximum low - level input v il v dd = +5v 0.8 v input current i in 0.05 a input capacitance c in 5 10 pf digital outputs minimum high - level output voltage v oh i source = 4ma 4.2 v maximum low - level output voltage v ol i sink = 4ma 0.2 v output cap acitance c out 10 15 pf tri - state output leakage current i oz 0.25 a
vmx51c1020 _________________________________________________________________________________________________________ www.ramtron.com page 5 of 80 analog inputs adci(0 - 3) input voltage range v adci 0 2.7 v adci(0 - 3) input resistance r adci 100 mohms (design) adci(0 - 3) input capacitance c adci 7 pf adci(0 - 3) input leakage current i adci tbd na channel - to - channel crosstalk - 72 (12 bit) db (design) analog output v ta= v adci(0 - 3) 10 ta output drive capabilities (maximum load resistance) others requires buffering 25m kohms current source isrc current dr ive ref isrc200 i isrc200 33 66 a (design) isrc current drive ref isrc800 i isrc800 133 500 a isrc feedback voltage 200mv ref isrc200 195 205 mv isrc feedback voltage 800mv ref isrc800 799 803 mv isrc output resistance r isrc 50 m ohms isrc outpu t capacitance c isrc 25 pf isrcin input reference resistance r resin 100 mohms isrcin input reference capacitance c resin 7 pf isrc stability drift 2.5 % allowable sensor capacitance between isrcin & isrcout 1000 pf allowable capacitance between isrcout & gnd 100 pf internal reference bandgap reference voltage 1.18 1.23v 1.28 v bandgap reference tempco 100 ppm/c external reference input impedance r xtvref 150 kohms pga pga gain adjustment 2.11 2.29 analog to digi tal converter external reference, ta=25c, fosc = 14.75mhz adc resolution 12 bits differential non linearity dnl 1.5 lsb integral non linearity inl - 1 +4 lsb full - scale error (gain error) all channels, adci(0 - 3) 4 lsb offset error all ch annels, adci(0 - 3) 1 lsb channel - to - channel mismatch all channels, adci(0 - 3) 1 lsb single channel 1 10k sampling rate 4 channels 1 2.5k hz uart1 differential transceiver compatible to j1708/ rs - 485/rs - 422 common mode input voltage vc i - 2 +7 v input impedance z in 1 mohms output drive current 30 ma differential input 100mv mv
vmx51c1020 _________________________________________________________________________________________________________ www.ramtron.com page 6 of 80 operational amplifier output impedance zout 20 mohms input resistance zin 36 gohms voltage gain g v 100 db unit gain bandwidth ugbw 5 mhz load resistance to ground 1 kohms load capacitance 40 pf slew rate sr 7 v/s (design) input offset voltage v io +/ - 2 mv input voltage range v i? 0 4 v (design) common mode rejection ratio cmrrdc dc 83 99 db cmrr1khz taken at 1khz 75 db design) power supply rejection ratio psrr taken at 1khz (20db/decade) - 75 (vdd) - 94 (vss) db (design) output voltage swing (rl=10k) v o (p - p) 25mv 4.975 v short circuit current to ground i ic 86 ma (design) digital potentiometers num ber of steps (8 - bit binary weighted) 256 steps maximum resistance 28k 30k 32k ohms minimum resistance 485 510 535 ohms step size 105 115 130 ohms inter channel matching 1 % temperature coefficient 0.16 %/c allowable current (dc) 5 ma inherent capacitance 3 pf digital switch switch on resistance 50 100 ohms (+/ - 10%) input capacitance 4 pf voltage range on pin 0 5 v allowable current (dc) 5 ma brown out / reset circuit brown - out circuit threshold 3.7 4.0 v res - pin internal pull - up 20 kohms
vmx51c1020 _________________________________________________________________________________________________________ www.ramtron.com page 7 of 80 detailed description the following sections will describe the vmx51c1020 ?s architecture and peripherals. f igure 5: i nterface d iagram for the vmx51c1020 vdd agnd vdda dgnd adci0 adci1 adci2 adci3 isrcin isrcout sdi sdo sck ss - cs0 - cs1 - cs2 - res- int0 int1 versa mix external a/d inputs current source reset i/os external interrupts spi interface +5v digital +5v analog t2in t2ex t0in t1in timers i/o compare and capture units inputs op-amp potentiometers pwm outputs pwm0 pwm1 pwm2 pwm3 pot1a pot1b pot2a pot2b opin+ opin- opout ccu0 ccu1 ccu2 osc0 osc1 digital switch sw1a sw1b uart 0 uart 1 differential transceiver uart1 diff. transceiver j1708/rs-485 / rs422 i2c interface sda uart 0 interface uart 1 interface scl cs3- f igure 6: m emory o rganization of the vmx51c1020 internal data memory space external data memory space internal program memory space 8051 compatible - processor 1kb sram sfr space - peripherals (direct addressing) 56kb flash memory 128 bytes ram (indirect addressing 03ffh 0000h 0000h dfffh 128 bytes ram (direct & indirect addressing) ffh 80h 7fh 00h ffh 80h memory organization figure 6 shows the memory organization of the vmx51c1020 . at power - up/reset, the code is executed from the 56kx8 flash memory mapped into the processor?s internal program space. a 1k b block of ram is also mapped into the external data memory of the vmx51c1020 . this block can be used as general - purpose scratch pad or storage memory. a 256 byte block of ram is mapped to the internal data memory space. this block of ram is broken into 2 sub - blocks, with the upper block accessible via indirect addressing and the lower block accessible via both direct and indirect addressing. the following figure describes the access t o the lower block of 128 bytes. f igure 7: l ower 128 b ytes b lock i nternal m emory m ap lower 128 bytes of internal data memory direct ram bit - addressable registers 7fh 30h 2fh 20h bank 3 1fh 18h bank 2 17h 10h bank 1 0fh 08h bank 0 07h 00h 00h 01h 10h 11h register bank select the value of the rs1, rs0 bits of psw sfr register (d0h) defines the selected r0 -r7 register bank the sfr (special function register) space is also mapped into the upper 128 bytes of internal data memory space. this sfr space is only accessible using direct - access. the sfr space provides the interface to all the on - chip peripherals. this interfacing is illustrated in figure 8.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 8 of 80 f igure 8: sfr o rganization internal data memory space sfr space - peripherals (direct addressing) adc control spi bus diff transceiver clock control peripheral interrupts mac i/o control i2c bus 8051 processor peripherals 80h ffh dual data pointers the vmx51c1020 includes two data pointers. the first data pointer (dptr0) is mapped into sfr locations 82h and 83h and the second data pointer (dptr1) mapped into sfr locations 84h and 85h. the sel bit in the data pointer select register, dps (sfr 86h), selects which data pointer is active. when sel = 0, instructions that use the data pointer will use dpl0 and dph0. when sel = 1, instructions that use the dptr will use dpl1 and dph1. sel is located in bit 0 of the dps ( sfr location 86h - the r emaining bits of sfr location 86h are un - used. all dptr - related instructions use the currently selected data pointer. in order to switch the active pointer, toggle the sel bit. the fastest way to do so is to use the increment instruction (inc dps). the use of the two data pointers can significantly increase the speed of moving large blocks of data because only one instruction is needed to switch from a source address and destination address. the sfr locations and register representations related to th e dual data pointers are outlined as follows : t able 3: (dph0) d ata p ointer h igh 0 - sfr 83 h 15 14 13 12 11 10 9 8 dph0 [7:0] t able 4: (dpl0) d ata p ointer l ow 0 - sfr 82 h 7 6 5 4 3 2 1 0 dpl0 [7:0] bit mnemon ic function 15 - 8 dph0 data pointer 0 msb 7 - 0 dpl0 data pointer lsb. t able 5: (dph1) d ata p ointer h igh 1 - sfr 85 h 15 14 13 12 11 10 9 8 dph1 [7:0] t able 6: (dpl1) d ata p ointer l ow 1 - sfr 84 h 7 6 5 4 3 2 1 0 dpl1 [7:0] bit mnemonic function 15 - 8 dph1 data pointer 1 msb. 7 - 0 dpl1 data pointer 1 lsb. t able 7: (dps) d ata p ointer s elect r egister - sfr 86 h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 sel bit mnemonic function 7 - 1 0 always zero 0 sel 0 = dptr0 is selected 1 = dptr1 is selected used to toggle between both data pointers mpage register the mpage register controls the upper 8 bits of the targeted address when the movx instruction is used for external ram data transfer. this allow s access to the entire external ram content without using the data pointer. t able 8: (mpage) m emory p age - sfr cf h 7 6 5 4 3 2 1 0 mpage [7:0] user flags the vmx51c1020 provides an sfr register that gives the user the ability to de fine software flags. each bit of this register is individually addressable. this register may also be used as a general - purpose storage location. thus, the user flag feature allows the vmx51c1020 to better adapt to each specific application. this register is located at sfr address f8h t able 9: (userflags) u ser f lag - sfr f8 h 7 6 5 4 3 2 1 0 uf7 uf6 uf5 uf4 uf3 uf2 uf1 uf0
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 9 of 80 instruction set all vmx51c1020 instructions are function and binary code compatible with the industry standard 8051. however, the timing of instruction s may be different. the following two tables describe the instruction set of the vmx51c1020 . t able 10: l egend for i nstruction s et t able symbol function a accumulator rn register r0 - r7 direct internal register address @ri internal register pointed to by r0 or r1 (except movx) rel two's complement offset byte bit direct bit address #data 8 - bit constant #data 16 16 - bit constant addr 16 16 - bit destination address addr 11 11 - bit destination address t able 11: vmx51c1020 i nstruction s et mnemonic description size (bytes) instr. cycles arithmetic instructions add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add data memory to a 1 2 add a , #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add data memory to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract data mem from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 2 inc dir ect increment direct byte 2 3 inc @ri increment data memory 1 3 dec a decrement a 1 1 dec rn decrement register 1 2 dec direct decrement direct byte 2 3 dec @ri decrement data memory 1 3 inc dptr increment data pointer 1 1 mul ab multiply a by b 1 5 div ab divide a by b 1 5 da a decimal adjust a 1 1 logical instructions anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and data memory to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct by te 2 3 anl direct, #data and immediate data to direct byte 3 4 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or data memory to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 3 orl dire ct, #data or immediate data to direct byte 3 4 xrl a, rn exclusive - or register to a 1 1 xrl a, direct exclusive - or direct byte to a 2 2 xrl a, @ri exclusive - or data memory to a 1 2 xrl a, #data exclusive - or immediate to a 2 2 xrl direct, a exclusive - o r a to direct byte 2 3 xrl direct, #data exclusive - or immediate to direct byte 3 4 clr a clear a 1 1 cpl a compliment a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rota te a right through carry 1 1 mnemonic description size (bytes) instr. cycles data transfer instructions mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move data memory to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 2 mov rn, direc t move direct byte to register 2 4 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 3 mov direct, rn move register to direct byte 2 3 mov direct, direct move direct byte to direct byte 3 4 mov direct, @ri move data me mory to direct byte 2 4 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to data memory 1 3 mov @ri, direct move direct byte to data memory 2 5 mov @ri, #data move immediate to data memory 2 3 mov dptr, #data16 move immediate 16 b it to data pointer 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (a8) to a 1 3 - 10 movx a, @dptr move external data (a16) to a 1 3 - 10 movx @ri, a move a to ext ernal data (a8) 1 4 - 11 movx @dptr, a move a to external data (a16) 1 4 - 11 push direct push direct byte onto stack 2 4 pop direct pop direct byte from stack 2 3 xch a, rn exchange a and register 1 2 xch a, direct exchange a and direct byte 2 3 xch a, @ri exchange a and data memory 1 3 xchd a, @ri exchange a and data memory nibble 1 3 branching instructions acall addr 11 absolute call to subroutine 2 6 lcall addr 16 long call to subroutine 3 6 ret return from subroutine 1 4 reti return from interr upt 1 4 ajmp addr 11 absolute jump unconditional 2 3 ljmp addr 16 long jump unconditional 3 4 sjmp rel short jump (relative address) 2 3 jc rel jump on carry = 1 2 3 jnc rel jump on carry = 0 2 3 jb bit, rel jump on direct bit = 1 3 4 jnb bit, rel j ump on direct bit = 0 3 4 jbc bit, rel jump on direct bit = 1 and clear 3 4 jmp @a+dptr jump indirect relative dptr 1 2 jz rel jump on accumulator = 0 2 3 jnz rel jump when accumulator not equal to 0 2 3 cjne a, direct, rel compare a, direct jne relat ive 3 4 cjne a, #data, rel compare a, immediate jne relative 3 4 cjne rn, #data, rel compare reg, immediate jne relative 3 4 cjne @ri, #data, rel compare ind, immediate jne relative 3 4 djnz rn, rel decrement register, jnz relative 2 3 djnz direct, re l decrement direct byte, jnz relative 3 4 bit operations clr c clear carry flag 1 1 clr bit clear direct bit 2 3 setb c set carry flag 1 1 setb bit set direct bit 2 3 cpl c complement carry flag 1 1 cpl bit complement direct bit 2 3 anl c,bit logic al and direct bit to carry flag 2 2 anl c, /bit logical and between /bit and carry flag 2 2 orl c,bit logical or bit to carry flag 2 2 orl c, /bit logical or /bit to carry flag 2 2 moc c,bit copy direct bit location to carry flag 2 2 mov bit,c copy ca rry flag to direct bit location 2 3 miscellaneous instruction nop no operation 1 1
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 10 of 80 special function registers the special function registers (sfrs) control several features of the vmx51c1020 . many of the vmx51c1020 sfrs are identical to the standa rd 8051 sfrs. however, there are additional sfrs that control the vmx51c1020 ?s specific peripheral features that are not available in the standard 8051. t able 12: s pecial f unction r egisters sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value p0 80h - - - - - - - - 1111 1111b sp 81h - - - - - - - - 0000 0111b dpl0 82h - - - - - - - - 0000 0000b dph0 83h - - - - - - - - 0000 0000b dpl1 84h - - - - - - - - 0000 0000b dph1 85h - - - - - - - - 0000 0000b dps 86h 0 0 0 0 0 0 0 sel 0000 0000b pcon 87h smod - - - gf1 gf0 stop idle 0000 0000b tcon* 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0000 0000b tmod 89h gate1 ct1 m11 m01 gate0 ct0 m10 m00 0000 0000b tl0 8ah - - - - - - - - 0000 0000b tl1 8bh - - - - - - - - 0000 0000b th0 8ch - - - - - - - - 0000 0000b th1 8dh - - - - - - - - 0000 0000b reserved 8eh 0000 0000b reserved 8fh 0000 0000b p1* 90h - - - - - - - - 1111 1111b ircon 91h t2exif t2if adcif/ compint3 macif/ compint2 i2cif/ compi nt1 spirxif/ compint0 spitxif reserved 0000 0000b analogpwren 92h opampen digpoten isrcsel isrcen taen adcen pgaen bgapen 0000 0000b digpwren 93h t2clken wdogen macen i2cen spien uart1diffen uart1en uart0en 0000 0000b clkdivctrl 94h softrst - - irqnorms pd mckdiv_3 mckdiv_2 mckdiv_1 mckdiv_0 0000 0000b adcclkdiv 95h - - - - - - - - 0000 1100b s0rell 96h - - - - - - - - 11011001b s0relh 97h 0 0 0 0 0 0 - - 0000 0011b s0con* 98h s0m0 s0m1 mpce0 r0en t0b8 r0b8 t0i r0i 0000 0000b s0buf 99h - - - - - - - - 0000 0000b ien2 9ah - - - - - - - s1ie 0000 0000b p0pincfg 9bh p07io p06io p05io p04io p0.3/rx1ine p0.2/tx1oe p0.1/t2exine p0.0/t2ine 0000 0000b p1pincfg 9ch p1.7 p1.6 p1.5 p1.4 p1.3/pwm3oe p1.2/pwm2oe p1.1/pwm1oe p1.0/pwm0oe 0000 0000b p2pincfg 9d h p2.7/sdien p2.6/sdoen p2.5/scken p2.4/ssen p2.3/cs0en p2.2/cs1en p2.1/cs2en p2.0/cs3en 0000 0000b p3pincfg 9eh p3.7/msclen p3.6/msdaen p3.5/t1inen p3.4/ccu1en p3.3/ccu0en p3.2/t0inen p3.1/rx0en p3.0/tx0en 0000 0000b portirqen 9fh p17ien p16ien p15ien p 14ien p13ien p12ien p11ien p10ien 0000 0000b p2* a0h - - - - - - - - 1111 1111b portirqstat a1h p17istat p16istat p15istat p14istat p13istat p12istat p11istat p10istat 0000 0000b adcctrl a2h adcirqclr xvrefcap 1 adcirq adcie onechan cont oneshot 0000 00 00b adcconvrlow a3h - - - - - - - - 0000 0000b adcconvrmed a4h - - - - - - - - 0000 0000b adcconvrhigh a5h - - - - - - - - 0000 0000b adcd0lo a6h - - - - - - - - 0000 0000b adcd0hi a7h adcd0hi_3 adcd0hi_2 adcd0hi_1 adcd0hi_0 0000 0000b ien0* a8h ea wdt t2ie s0ie t1ie int1ie t0ie int0ie 0000 0000b adcd1lo a9h - - - - - - - - 0000 0000b adcd1hi aah adcd1hi_3 adcd1hi_2 adcd1hi_1 adcd1hi_0 0000 0000b adcd2lo abh - - - - - - - - 0000 0000b adcd2hi ach adcd2hi_3 adcd2hi_2 adcd2hi_1 adcd2hi_0 0000 0000b adcd3lo adh - - - - - - - - 0000 0000b adcd3hi aeh adcd3hi_3 adcd3hi_2 adcd3hi_1 adcd3hi_0 0000 0000b reserved afh 0000 0000b p3* b0h - - - - - - - - 1111 1111b reserved b1h 1101 0001b reserved b2h 0000 0000b bgapcal b3h - - - - - - - - cal. vector pgacal b4h - - - - - - - - cal. vector inmuxctrl b5h - adcinsel_2 adcinsel_1 adcinsel_0 ainen_3 ainen_2 ainen_1 ainen_0 0000 0000b outmuxctrl b6h - - - - - taoutsel_2 taoutsel_1 taoutsel_0 0000 0000b switchctrl b 7h - - - - switch1_3 switch1_2 switch1_1 switch1_0 0000 0000b ip0* b8h uf8 wdtstat ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 0000 0000b ip1 b9h - - ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 0000 0000b digpot1 bah - - - - - - - - 0000 0000b
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 11 of 80 sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value digpot2 bbh - - - - - - - - 0000 0000b isrccal1 bch pgacal0 isrccal1_6 isrccal1_5 isrccal1_4 isrccal1_3 isrccal1_2 isrccal1_1 isrccal1_0 cal. vector isrccal2 bdh - isrccal2_6 isrccal2_5 isrccal2_4 isrccal2_3 isrccal2_2 isrccal2_1 isrccal2_0 cal. vector s1rell beh - - - - - - - - 0000 0000b s1relh bfh - - - - - - - - 0000 0000b s1con* c0h s1m reserved mpce1 r1en t1b8 r1b8 t1i r1i 0000 0000b s1buf c1h - - - - - - - - 0000 0000b ccl1 c2h - - - - - - - - 0000 0000b cch1 c3h - - - - - - - - 0000 0000b ccl2 c4h - - - - - - - - 0000 0000b cch2 c5h - - - - - - - - 0000 0000b ccl3 c6h - - - - - - - - 0000 0000b cch3 c7h - - - - - - - - 0000 0000b t2con* c8h t2ps t2psm t2size t2rm1 t2rm0 t2cm t2in1 t2in0 0000 0000b ccen c9h cocah3 cocal3 cocah2 cocal2 cocah1 cocal1 cocah0 c ocal0 0000 0000b crcl cah - - - - - - - - 0000 0000b crch cbh - - - - - - - - 0000 0000b tl2 cch - - - - - - - - 0000 0000b th2 cdh - - - - - - - - 0000 0000b reserved ceh mpage cfh - - - - - - - - 0000 0000b psw* d0h cy ac f0 rs1 rs0 ov re served p 0000 0001b reserved d1h to d7 d1h - d4h =ffh d5h - d7h = 00h u0baud d8h baudsrc - - - - - - - 0000 0000b wdtrel d9h pres wdtrel_6 wdtrel_5 wdtrel_4 wdtrel_3 wdtrel_2 wdtrel_1 wdtrel_0 0000 0000b i2cconfig dah i2cmaskid i2crxovie i2crxdavi e i2ctxempie i2cmanack i2cackmode i2cmstop i2cmaster 0000 0010b i2cclkctrl dbh - - - - - - - - 0000 0000b i2cchipid dch i2cid_6 i2cid_5 i2cid_4 i2cid_3 i2cid_2 i2cid_1 i2cid_0 i2cwid 0100 0010b i2cirqstat ddh i2cgotstop i2cnoack i2csda i2cdatack i2cidle i2crxov i2crxav i2ctxemp 0010 1001b i2crxtx deh - - - - - - - - 0000 0000b reserved dfh 0000 0000b acc* e0h - - - - - - - - 1110 0000b spirx3tx0 e1h - - - - - - - - 0000 0000b spirx2tx1 e2h - - - - - - - - 0000 0000b spirx1tx2 e3h - - - - - - - - 0000 0000b spirx0tx3 e4h - - - - - - - - 0000 0000b spictrl e5h spick_2 spick_1 spick_0 spics_1 spics_0 spickph spickpol spima_sl 0000 0001b spiconfig e6h spicslo - fsoncs3 spi load - spirxovie spirxavie spitxempie 0000 0000b spisize e7h - 0000 0111b ien1* e8h t2exie swdt adcpcie macovie i2cie spirxovie spiteie reserved 0000 0000b spiirqstat e9h - - spitxempto spislavesel spisel spiov spirxav spitxemp 00011001b reserved eah 0000 0000b macctrl1 ebh loadprev prevmode ovmode ovrdva l addsrc_1 addsrc_0 mulcmd_1 mulcmd_0 0000 0000b macc0 ech - - - - - - - - 0000 0000b macc1 edh - - - - - - - - 0000 0000b macc2 eeh - - - - - - - - 0000 0000b macc3 efh - - - - - - - - 0000 0000b b* f0h - - - - - - - - 0000 0000b macctrl2 f1h macclr 2_2 macclr2_1 macclr2_0 macov32ie - - macov16 macov32 0000 0000b maca0 f2h - - - - - - - - 0000 0000b maca1 f3h - - - - - - - - 0000 0000b macres0 f4h - - - - - - - - 0000 0000b macres1 f5h - - - - - - - - 0000 0000b macres2 f6h - - - - - - - - 0000 0 000b macres3 f7h - - - - - - - - 0000 0000b userflags* f8h uf7 uf6 uf5 uf4 uf3 uf2 uf1 uf0 0000 0000b macb0 f9h - - - - - - - - 0000 0000b macb1 fah - - - - - - - - 0000 0000b macshiftctrl fbh shiftmode alshstyle shiftampl_5 shiftampl_4 shiftampl_3 sh iftampl_2 shiftampl_1 shiftampl_0 0000 0000b macprev0 fch - - - - - - - - 0000 0000b macprev1 fdh - - - - - - - - 0000 0000b macprev2 feh - - - - - - - - 0000 0000b macprev3 ffh - - - - - - - - 0000 0000b * bit addressable
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 12 of 80 peripheral activ ation control digital peripheral power enable in order to save power upon reset, many of the digital peripherals of the vmx51c1020 are not activated. the peripherals affected by this feature are: o timer 2 / port1 o watchdog timer o mult/accu unit o i2 c interface o spi interface o uart0 o uart1 o differential transceiver before using any of the above - listed peripherals, they must first be enable d by setting the corresponding bit of the digpwren sfr register to 1. the same rule applies when access ing a given peripheral? s sfr register (s) . the targeted peripheral must have been powered on (enabled) first , o therwise the sfr register content will be i gnored the following table shows the structure of the digpwren register. t able 13: (digpwren) d igital p eripherals p ower e nable r egister - sfr 93 h 7 6 5 4 t2clken wdogen macen i2cen 3 2 1 0 spien uart1diffen uart1en uart0en bit mnemonic function 7 t2clken timer 2 / pwm enable 0 = timer 2 clk stopped 1 = timer 2 clk running 6 wdogen watchdog enable 0 = watchdog disable 1 = watchdog enable 5 macen 1 = mult/accu unit enable 0 = mult/accu unit disable 4 i2cen 1= i2c interface enable 0 = i2c interface disable this bit is merged with clk stop bit 3 spien 1 = spi interface is enable 0 = spi interface i s disable 2 uart1diffen uart1 differential mode 0 = disable 1 = enable 1 uart1en 0 = uart1 disable 1 = uart1 enable 0 uart0en 0 = uart0 disable 1 = uart0 enable analog peripheral power enable the analog peripherals , specifically, the op - amp digita l potentiometer , current source and analog to digital converter , have a shared dedicated register used for enabling and disabling these peripherals . by default, th e se peripherals are powered down when the device is reset. t able 14: (an alogpwren) a nalog p eripherals p ower e nable r egister - sfr 92 h 7 6 5 4 opampen digpoten isrcsel isrcen 3 2 1 0 taen adcen pgaen bgapen bit mnemonic function 7 opampen 1 = user op - amp enable 0 = user op - amp disable 6 digpoten 1 = digital potentiomete r and switch enable 0 = digital potentiometer and switch disable 5 isrcsel 0 = isrc with 200mv feedback 1 = isrc with 200mv feedback 4 isrcen 1 = isrc output enable 0 = isrc output disable 3 taen 1 = ta output enable 0 = ta output disable 2 adcen 1 = adc enable 0 = adc disable 1 pgaen 1 = pga enable 0 = pga disable 0 bgapen 1 = bandgap enable 0 = bandgap disable note : the sfr registers associated with all analog peripherals are activated when one or more analog peripherals are enabled.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 13 of 80 general p urpose i/o the vmx51c1020 provide s 28 general - purpose i/o pins. the i/os are shared with digital peripherals and can be configured individually. at reset, all the vmx51c1020 i/o ports are configured as input s the i/o ports are bi - directional and the cpu can write or read data through any of these ports. i/o port structure the vmx51c1020 i/o port structure is shown in the following figure. f igure 9 ? i/o port structure i/o ttl driver oe vcc vcc i/o control logic each i/o pin includes pull - up circuitry (represented by the internal pull - up resistor) and a pair of internal protection diodes connected to vcc and ground , provid ing esd protection. the i/o operational configuration is defined in the i/o control logic block. i/o port drive capability each i/o port pin, when configured as an output is able to source or sink up to 4ma. the following graphs show typical i/o output voltage vs. source and i/o output voltage versus sink current. f igure 10: t ypical i/o v out vs . source current i/o output voltage (volts) i/o current source (ma) 4.50 4.60 4.70 4.80 4.90 5.00 0.0 2.0 4.0 6.0 8.0 10.0 f igure 11: t ypical i/o v out v s . sink current i/o output voltage (volts) i/o current sink (ma) 0.00 0.10 0.20 0.30 0.40 0.50 0.0 2.0 4.0 6.0 8.0 10.0 the maximum recommended driving current of a single i/o on a given port is 10ma. the recommended limit when more than one i/o on a given port is driving current is 5ma on each i/o. the total current drive of all i/o ports should be limi ted to 40ma the following figure shows typical i/o rise time when driving a 20pf capacitive load. in th is case, rise time is about 14ns. f igure 12: i/o r ise t ime with a 20 p f l oad
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 14 of 80 input voltage vs. ext. device sink the i/os of the vmix, when configured as input s , include an internal pull - up resistor made of a transistor that ensures the level present at the input is stable when the i/o pin is unconnected. due to the presence of the pull - up resistor on the digital inputs, the exte rnal device driving the i/o must be able to sink enough current to bring the i/o pin low . the following figure shows the vmx51c1020 input port voltage vs. external device sink current. f igure 13: i nput port v oltage vs . ext device sink cur rent i/o input voltage (volts) ext. device sink current (ua) 0.0 1.0 2.0 3.0 4.0 5.0 0 20 40 60 80 100 120 140 160 180 i/o port configuration registers the vmx51c1020 ?s i/o port operation is controlled by two sets of four registers which are: o the port pin configuration registers o the port access registers the port pin configuration registers combined with specific peripheral c onfiguration will define if a given pin acts as a general purpose i/o or if it provides alternate peripheral functionality. before using a peripheral that is shared with i/os, the pin corresponding to the peripheral output must be configured as an output and the pins that are shared with the peripheral inputs must be configured as input s . the following registers are used to configure each of the ports as either general - purpose input, output or alternate peripheral function . . for example, when bit 5 o f port 2 is configured as an output, it will output the sck signal if the spi interface is enabled and working. the only exception to this rule is the i 2 c clock and data bus signals. in these two cases, the vmx51c1020 configures the pins automatically as inputs or outputs. the p0pincfg register controls the i/o access to uart1, the timer 2 input and output , as well as defines the direction of the p0 when used as general purpose i/o. t able 15: (p0pincfg) p ort 0 p ort c onfiguration r egis ter - sfr 9b h 7 6 5 4 p07io p06io p05io p04io 3 2 1 0 p0.3/rx1ine p0.2/tx1oe p0.1/t2exine p0.0/t2ine bit mnemonic function 7:4 p0xio unavailable on vmx51c1020 3 p0.3/rx1ine 0: general purpose input or uart1 rx 1: general purpose output when usi ng uart1 you must set this bit to 0. 2 p0.2/tx1oe 0: general purpose input 1: general purpose output or uart1 tx when using uart1 you must set this bit to 1. 1 p0.1/t2exine 0: general purpose input or timer 2 ex 1: general purpose output when usin g timer 2ex input you must set this bit to 0. 0 p0.0/t2ine 0: general purpose input or timer 2 in 1: general purpose output when using timer 2 input you must set this bit to 0.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 15 of 80 the p1pincfg register controls the access from the pwm to the i/o pins as well as defines the direction of the p1 when the pwm?s are not used. t able 16: (p1pincfg) p ort 1 p ort c onfiguration r egister - sfr 9c h 7 6 5 4 p1.7 p1.6 p1.5 p1.4 3 2 1 0 p1.3/pwm3oe p1.2/pwm2oe p1.1/pwm1oe p1.0/pwm0oe bit mnemonic function 7 p1.7 0: general purpose input 1: general purpose output 6 p1.6 0: general purpose input 1: general purpose output 5 p1.5 0: general purpose input 1: general purpose output 4 p1.4 0: general purpose input 1: general purpose outp ut 3 p1.3/pwm3oe 0: general purpose input 1: general purpose output or pwm bit 3 output when using pwm you must set this bit to 1. 2 p1.2/pwm2oe 0: general purpose input 1: general purpose output or pwm bit 2 output when using pwm you must set this bit to 1 1 p1.1/pwm1oe 0: general purpose input 1: general purpose output or pwm bit 1 output when using pwm you must set this bit to 1 0 p1.0/pwm0oe 0: general purpose in put 1: general purpose output or pwm bit 0 output when using pwm you must set this b it to 1 the p2pincfg register controls the i/o access to spi interface and defines the direction of the p2 when used as general purpose i/o t able 17: (p2pincfg) p ort 2 p ort c onfiguration r egister - sfr 9d h 7 6 5 4 p2.7/sdien p2. 6/sdoen p2.5/scken p2.4/ssen 3 2 1 0 p2.3/cs0en p2.2/cs1en p2.1/cs2en p2.0cs3en bit mnemonic function 7 p2.7/sdien 0: general purpose input or sdi 1: general purpose output when using spi you must set this bit to 0. 6 p2.6/sdoen 0: general pur pose input 1: general purpose output or sdo when using spi you must set this bit to 1. 5 p2.5/scken 0: general purpose input or sck 1: general purpose output when using spi you must set this bit to 0. 4 p2.4/ssen 0: general purpose input or slave select 1: general purpose output when using spi ss you must set this bit to 0. 3 p2.3/cs0en 0: general purpose input 1: general purpose output or chip select bit 0 output when using spi cs0 you must set this bit to 1. 2 p2.2/cs1en 0: gene ral purpose input 1: general purpose output or chip select bit 1 output when using spi cs1 you must set this bit to 1. 1 p2.1/cs2en 0: general purpose input 1: general purpose output or chip select bit 2 output when using spi cs2 you must set this bit to 1. 0 p2.0/cs3en 0: general purpose input 1: general purpose output or chip select bit 3 output when using spi cs3 you must set this bit to 1.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 16 of 80 the p3pincfg register controls i/o access to uart0, the i2c interface, capture compare inpu t0 and 1, timer 0 and timer 1 inputs as well as defines the direction of p3 when used as general purpose i/o t able 18: (p3pincfg) p ort 3 p ort c onfiguration r egister - sfr 9e h 7 6 5 4 p3.7/msclen p3.6/msdaen p3.5/t1ine n p3.4/ccu1e n 3 2 1 0 p3.3/ ccu0en p3.2/ t0inen p3.1/ rx0en p3.0/ tx0en bit mnemonic function 7 p3.7/msclen 0: general purpose input 1: general purpose output or master i2c scl output when using the i2c you must set this bit to 1. 6 p3.6/msdaen 0: general purpose input 1: general purpose output or master i2c sda when using the i2c you must set this bit to 1. 5 p3.5/t1inen 0: general purpose input or timer1 input 1: general purpose output when using timer 1 you must set this bit to 0. 4 p3.4/ccu1en 0: ge neral purpose input or ccu1 input 1: general purpose output when using the compare and capture unit you must set this bit to 0. 3 p3.3/ ccu0en 0: general purpose input or ccu0 input 1: general purpose output when using the compare and capture uni t you must set this bit to 0. 2 p3.2/ t0inen 0: general purpose input or timer 0 input 1: general purpose output when using timer 0 you must set this bit to 0. 1 p3.1/ rx0en 0: general purpose input or uart0 rx 1: general purpose output when usin g uart0 you must set this bit to 0. 0 p3.0/ tx0en 0: general purpose input 1: general purpose output or uart0 tx when using uart0 you must set this bit to 1. using general purpose i/o ports the vmx51c1020 ?s 28 i/os are grouped in to four ports. for each port an sfr register location is defined. those registers are bit addressable providing the ability to control the i/o lines individually. when the port pin configuration register value defines the pin as an output, the value written into the port r egister will be reflected at the pin level. reading the i/o pin configured as input is done by reading the content s of its associated port register. t able 19: p ort 0 - sfr 80 h 7 6 5 4 3 2 1 0 p0 [7:0] p ort 1 - sfr 90 h 7 6 5 4 3 2 1 0 p1 [7:0] p ort 2 - sfr a0 h 7 6 5 4 3 2 1 0 p2 [7:0] p ort 3 - sfr b0 h 7 6 5 4 3 2 1 0 p3 [7:0] bit mnemonic function 7 - 0 p0, 1, 2, 3 when the port is configured as an output, setting a port pin to 1 will make the corresponding pin to output logic high. when set to 0, the corresponding pin will set a logic low. i/o usage example the following example demonstrates the configuration of the vmx51c1020 i/os. // --------------------------------------------------------------------------- //this exampl e continuously reads the p0 and writes its contents into //p1 and it toggle p2 and p3. // --------------------------------------------------------------------------- #pragma tiny #pragma unsignedchar #include at 0x0000 void main (void) { digpwren = 0x80; // enable timer 2 to activate p1 //output p1pincfg = 0x00; // configure all p0 as input p1pincfg = 0xff; //configure p1 as output p2pincfg = 0xff; //configure p2 as output p3pincfg = 0xff; //configure p3 as output wh ile(1) { p1 = p0; //write p0 into p1 p2 = ~p2; //toggle p2 & p3 p3 = ~p3; } }//end of main() function using port1.0 - 3 as general purpose output port1.0 - p1.3 can be used as standard digital outputs. however, in order to do this , the timer 2 clock must be enabled by setting the
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 17 of 80 t2clken bit of the digpwren register. in addition, the timer 2 ccen register must also have the reset value. interrupt on port1 change feature the vmx51c1020 includes a n interrupt on port1 change feature . this feature can be used to monitor the activity on each i/o port1 pin (individually) and trigger an interrupt when the state of the pin on which this feature has been activated changes. this is equivalent to having eight individual external int errupt inputs. the interrupt on port1 change shares the interrupt vector of the adc peripheral at address 006bh. see the interrupt section for more details on how to use this feature.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 18 of 80 mult/accu - multiply accumulator unit the vmx51c1020 includes a hardware based multiply - accumulator unit which provides the user the ability to perform fast and complex arithmetic operations. mult/accu features : o hardware calculation engine o calculation result is ready as soon as the input registers are loaded o signed mathematical calculations o unsigned math operations are possible if the mul engine operands are limited to 15 - bits in size o auto/manual reload of mac_res o enhanced vmx51c1020 mult/accu unit o easy implementation of complex math operations o 16 - bit and 32 - bit ove rflow flag o 32 - bit overflow can raise an interrupt o mult/accu operand registers can be cleared individually or all together o overflow flags can be configured to stay active until manually cleared o can store and use results from previous operations the mult/ accu can be configured to perform the following operations: f igure 13: vmx51c1020 mult/accu o peration (maca x macb) + macc = mac_result (maca x macb) + 0 = mac_result (maca x macb) + mac_prev = mac_result (maca x maca) + macc = mac_result (maca x maca) + 0 = mac_result (maca x maca) + mac_prev = mac_result (maca x mac_prev(16lsb) + macc = mac_result (maca x mac_prev(16lsb) + 0 = mac_result (maca x mac_prev(16lsb) + mac_prev = mac_result add32 + add32 mult16 + add32 (maca, macb) + macc = mac_result where maca (multiplier), macb (multiplicand), macacc (accumulator) and macresult (result) are 16, 16, 32 and 32 bits, resp ectively. mult/accu control registers with the exception of the barrel shifter, the mult/accu unit operation is controlled by two sfr registers: o the macctrl1 o the macctrl2 the following two tables describe the details of these control registers. t abl e 20: (macctrl1) mult/accu u nit c ontrol r egister - sfr eb h 7 6 5 4 loadprev prevmode ovmode ovrdval 3 2 1 0 addsrc [1:0] mulcmd [1:0] bit mnemonic function 7 loadprev macprev manual load control 1 = manual load of the macprev r egister content if prevmode = 1 6 prevmode loading method of macprev register 0 = automatic load when maca0 is written. 1 = manual load when 1 is written into loadprev 5 ovmode 0 = once set by math operation, the ov16 and ov32 flag will remain set until the overflow condition is removed. 1= once set by math operation, the ov16 and ov32 flag will stay set until it is cleared manually. 4 ovrdval 0 = the value on macres is the calculation result. 1 = the value on macres is the 32lsb of the macres when the ov32 overflow occurred 3:2 addsrc[1:0] 32 - bit addition source b input 00 = 0 (no add) 01 = c (std 32 - bit reg) 10 = res ? 1 11 = c (std 32 - bit reg) a input 00=multiplication 01=multiplication 10=multiplication 11= concatenation of {a, b} for 32 - bit addi tion 1:0 mulcmd[1:0] multiplication command 00 = maca x macb 01 = maca x maca 10 = maca x macprev (16 lsb) 11 = maca x macb
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 19 of 80 t able 21: (macctrl2) mult/accu u nit c ontrol r egister 2 - sfr f1 h 7 6 5 4 macclr2 [2:0] macov32ie 3 2 1 0 - - macov16 macov32 bit mnemonic function 7:5 macclr[2:0] mult/accu register clear 000 = no clear 001 = clear maca 010 = clear macb 011 = clear macc 100 = clear macprev 101 = clear all mac regs + overflow flags 110 = clear overflow flags only 4 macov 32ie mult/accu 32 - bit overflow irq enable 3 - - 2 - - 1 macov16 16 - bit overflow flag 0 = no 16 overflow 1 = 16 - bit mult/accu overflow occurred 0 macov32 32 - bit overflow flag 1 = 32 - bit mult/accu overflow this automatically loads the mac32ov register. the macov32 can generate a mult/accu interrupt when enabled. mult/accu unit data registers the mult/accu data registers include operand and result registers that serve to store the numbers being manipulated in mathematical operations. some of these regi sters are uniquely for addition (such as macc) while others can be used for all operations. the mult/accu operation registers are represented below. maca and macb multiplication (addition) input registers the maca and macb register serve as 16 - bit input o perands when performing multiplication. when the mult/accu is configured to perform 32 - bit addition, the maca and the macb registers are concatenated to represent a 32 - bit word. in that case the maca register contains the upper 16 - bit of the 32 - bit ope rand and the macb contains the lower 16 - bit t able 22: (maca0) mult/accu u nit a o perand , l ow b yte - sfr f2 h 7 6 5 4 3 2 1 0 maca0 [7:0] bit mnemonic function 7:0 maca0 lower segment of the maca operand t able 23: (maca1) mult/accu u nit a o perand , h igh b yte - sfr f3 h 7 6 5 4 3 2 1 0 maca1 [15:8] bit mnemonic function 15:8 maca1 upper segment of the maca operand t able 24: (macb0) mult/accu u nit b o perand , l ow b yte - sfr f9 h 7 6 5 4 3 2 1 0 macb0 [7:0] bit mnemonic function 7:0 macb0 lower segment of the macb operand t able 25: (macb1) mult/accu u nit b o perand , h igh b yte - sfr fa h 7 6 5 4 3 2 1 0 macb1 [7:0] bit mnemonic function 7:0 macb1 upper segment of the macb operand macc input register the macc register is a 32 - bit register used to perform 32 - bit addition. it?s possible to substitute the macprev register for the macc register or 0 in the 32 - bit addition. t able 26: (macc0) mult/acc u u nit c o perand , l ow b yte - sfr ec h 7 6 5 4 3 2 1 0 macc0 [7:0] bit mnemonic function 7:0 macc0 lower segment of the 32 - bit addition register t able 27: (macc1) mult/accu u nit c o perand , b yte 1 - sfr ed h 7 6 5 4 3 2 1 0 macc1 [1 5:8] bit mnemonic function 15:8 macc1 lower middle segment of the 32 - bit addition register t able 28: (macc2) mult/accu u nit c o perand , b yte 2 - sfr ee h 7 6 5 4 3 2 1 0 macc2 [23:16] bit mnemonic function 23:16 macc2 upper middl e segment of the 32 - bit addition register
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 20 of 80 t able 29: (macc3) mult/accu u nit c o perand , h igh b yte - sfr ef h 7 6 5 4 3 2 1 0 macc3 [31:24] bit mnemonic function 31:24 macc3 upper segment of the 32 - bit addition register macres res ult register the macres register, which is 32 - bit s wide, contains the result of the mult/accu operation. in fact, the macres register is the output of the barrel shifter. t able 30: (macres0) mult/accu u nit r esult , l ow b yte - sfr f4 h 7 6 5 4 3 2 1 0 macres0 [7:0] bit mnemonic function 7:0 macres0 lower segment of the 32 - bit mult/accu result register t able 31: (macres1) mult/accu u nit r esult , b yte 1 - sfr f5 h 7 6 5 4 3 2 1 0 macres1 [15:8] bit mnemonic functi on 15:8 macres1 lower middle segment of the 32 - bit mult/accu result register t able 32: (macres2) mult/accu u nit r esult , b yte 2 - sfr f6 h 7 6 5 4 3 2 1 0 macres2 [23:16] bit mnemonic function 23:16 macres2 upper middle segment of the 32 - bit mult/accu result register t able 33: (macres3) mult/accu u nit r esult , h igh b yte - sfr f7 h 7 6 5 4 3 2 1 0 macres3 [31:24] bit mnemonic function 31:24 macres3 upper segment of the 32 - bit mult/accu result register macpre v register the macprev register provides the ability to automatically or manually save the content s of the macres register and re - inject it into the calculation. this feature is especially useful in applications where the result of a given operation serve s as one of the operand s of the next one. as mentioned previously , there are two ways to load the macprev register controlled by the prevmode bit value: prevmode = 0: auto macprev load, by writing into the maca0 register. selected when prevmode = 0. prevmode = 1: manual load of macprev when the loadprev bit is set to 1 a good example using the auto loading of the macprev feature is the implementation of a fir filter. in that specific case, it is possible to save a total of 8 mov operations per tap c alculation. t able 34: (macprev0) mult/accu u nit p revious o peration r esult , l ow b yte - sfr fc h 7 6 5 4 3 2 1 0 macprev0 [7:0] bit mnemonic function 7:0 macprev0 lower segment of 32 - bit mult/accu previous result register t able 35: (macprev1) mult/accu u nit p revious o peration r esult , b yte 1 - sfr fd h 7 6 5 4 3 2 1 0 macprev1 [7:0] bit mnemonic function 15:8 macprev1 lower middle segment of 32 - bit mult/accu previous result register t able 36: (macprev2) mult/accu u nit p revious o peration r esult , b yte 2 - sfr fe h 7 6 5 4 3 2 1 0 macprev2 [15:8] bit mnemonic function 23:16 macprev2 upper middle segment of 32 - bit mult/accu previous result register t able 37: (macpre v3) mult/accu u nit p revious o peration r esult , h igh b yte - sfr ff h 7 6 5 4 3 2 1 0 macprev3 [7:0] bit mnemonic function 31:24 macprev3 upper segment of 32 - bit mult/accu previous result register
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 21 of 80 f igure 14: vmx51c1020 mult/accu f unctional d iagram maca1 (msb) maca0 (lsb) macb1 (msb) macb0 (lsb) sfr registers macc3 (msb) macc2 macc1 macc0 (lsb) maca macb mul (signed) mulcmd add msb add lsb addsrc macc ov32 ov16b shift ovrdval macres macprev maca0 load loadprev prevmode mac32ov (stored) macres (sfr regs) ov32f rst 1 load ovclr shiftmode ov32 ov32f / irq rst 1 ovmode ov32 ov16a+b ov16f rst 1 ovmode ov16a+b ov16a 0 (16 lsb) macres2 macres3 (msb) macres1 macres0 (lsb) sfr registers macres2 macres3 (msb) macres1 macres0 (lsb) sfr registers macshiftctrl mac32ov3 (msb) mac32ov2 mac32ov1 mac32ov0 (lsb) macctrl2 mac control sfr macshiftctrl mac32ov3 (msb) mac32ov2 mac32ov1 mac32ov0 (lsb) macctrl2 mac control sfr macshiftctrl mac32ov3 (msb) mac32ov2 mac32ov1 mac32ov0 (lsb) macctrl1 macctrl2 mac control sfr mac32ov3 (msb) mac32ov2 mac32ov1 mac32ov0 (lsb) macctrl2 addsrc b b a a concatenation (a,b) the above block diagram shows the interaction between the registers and the other components that comprise the mult/accu unit on the vmx51c1020 .
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 22 of 80 mult/accu barrel shifter the mult/accu includes a 32 - bit barrel shifter at t he output of the 32 - bit addition unit. the barrel shifter can perform right/left shift operations in one cycle, which is useful for scal ing the output result of the mult/accu. the shift range is adjustable from 0 to 16 in both directions . the ?shifted? add ition unit output can be routed to the : o macres o macprev o macov32 the barrel shifter can perform both arithmetic and logical shifts: the shift left operation can be configured as an arithmetic or logical shift. in the later, the sign bit is discarded. t able 38: (macshiftctrl) mult/accu u nit b arrel s hifter c ontrol r egister - sfr fb h 7 6 5 4 3 2 1 0 shiftmode alshstyle shiftampl [5:0] bit mnemonic function 7 shiftmode 0 = logical shift 1 = arithmetic shift 6 alshstyle arithmetic shift left style 0= arithmetic left shift: logical left 1= arithmetic left shift: keep sign bit 5:0 shiftampl[5:0] shift amplitude 0 to 16 (5 bits to provide 16 bits shift range) neg. number = shift right (2 complements) pos. number = shift left mult/accu unit setup and ov32 interrupt example in order to use the mult/accu unit, the user must first set up and configure the module. the following provides setup code examples . the first part of the code is the interrupt setup and modul e configuration, whereas the second part is the interrupt function itself . sample c code for mult/accu unit interrupt setup and module configuration: // --------------------------------------------------------------------------- // sample c code to setup t he mult/accu unit // --------------------------------------------------------------------------- // --- program initialisation omitted? (?) void main(void){ // mult/accu setup ien0 |= 0x80; // enable all interrupts ien1 |= 0x10; // enable mult/accu interr upt digpwren |= 0x20; // enable mult/accu unit macctrl1 = 0x0c; // {a,b}+c macctrl2 = 0x10; // enable int overflow_32 // mult/accu example use maca0 = 0xff; maca1 = 0x7f; macb0 = 0xff; macb1 = 0xff; macc0 = 0xff; macc1 = 0xff; macc2 = 0xff; macc3 = 0x7f; // --- as soon as the mac input registers are loaded the result is available in the macresx registers. }//end of main // --------------------------------------------------------------------------------- // mac 32 bit overflow interrupt function vo id int_5_mac (void) interrupt 12 { ien0 &= 0x7f; // disable all interrupts //put mac 32 bit overflow interrupt code here.*/ //note that when a 32bit overflow occurs, the 32 least significant bit of the current //result are stored into the mac32ovx regi sters and can be read at the location of macresx by setting to 1 the ovrdval bit of the macctrl register ircon &= 0xef; // clear flag (iex5) ien0 |= 0x80; // enable all interrupts } // ------------------------------------------------------------------- ------------- mult/accu application example: fir filter function the following asm code shows the implementation of a fir filter computation function for one iteration, the data shifting operation and the definition of the fir filter coefficient table. t he fir computation is simple to implement, however , it is quite demanding in terms of processing power. for each new data point, the multiplication with associated coefficients + addition operation must be performed n times (n=number of filter t apps). d ue to being hardware based and including features such as automatic reload of the result of the previous operation, the vmx51c1020 mult/accu unit is very efficient for performing operations such as fir filter computation. in the code example below, the computefir loop forms the heart of the fir computation and it is clear that u s e of the mult/accu unit implies very few instructions being required for mathematical operations. t he net result is a dramatic performance improvement when compar ed with manual c alculations done solely via the standard 8051 instruction set.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 23 of 80 vmx51c1020 fir filter example the example below shows how to use the mult/accu unit of the vmx51c1020 to perform fir filter computing. in order to minimize the example size, only the fir com puting function and the coefficient table are presented. ; ---------------------------------------------------- // ;** fir filter computing function // ; --------------------------------------------------- // fircompute: mov r0,#npointsbasead rs ;input adc raw data ;at xn locations... ;saving acquired data from calling function into ram for computation mov varh,datah mov varl,datal mov @r0,varh ;(msb) inc r0 mov @r0,varfl ;(lsb) ;** prepare to compute yn... ;***define base adrs of input values mov r0,#npointsbaseadrs ;***define base address of coefficients mov r1,#coefbaseadrs mov r7,#npoints ;define counter ;***configure the mult/accu unit as follow: mov macctrl,#00001000b ;bit7 loadprev = 0 no manual previou s result ;bit6 prevmode = 0 automatic previous result save when ; mult/accua0 is loaded ;bit5 ovmode = 0 overflow flag remains on until overflow ; condition exist ;bit4 ovrdval = 0 the value of macres is the calculation ; result ;bit3:2 addsrc = 10 macprev is the addition source ;bit1:0 mulcmd = 00 mul operation = macaxmacb ;**clear the mult/accu registers content mov macctrl2,#0a0h ;** compute yn... computefir: movmacb1,@r1 ;put a given coefficient into ;mult/accub inc r1 mov macb0,@r1 inc r1 mov maca1,@r0 ; put a given xn input into inc r0 mov maca0,@r0 ;this last instruction load the macprev register for next operation inc r0 djnz r7,computefir ;do the computation for n taps ;*** second part ; ------------- ------------------------------------------------------------------------------------------ // ;** shift previous input values to let place for next one... ; ----------------------------------------------------------------------------------------------------- -- // shiftpast: mov r7,#(npoints - 1)*2 ;define # of datashift ;to perform (n - 1)*2 ;***compute first fetch address mov r0,#(npointsbaseadrs - 1 + 2*(npoints - 1)) ;***compute first destination address mov r1,#(npointsbaseadrs + 1 + 2*(npoints - 1)) shif tloop: mov a,@r0 ;shift given lsb input... mov @r1,a ;to next location dec r0 ;prepare pointer for moving lsb dec r1 djnz r7,shiftloop ;** perform transformation of yn here and put into binh, binl ;** in this case the coefficients have been multiplied by 65536 ;** so the result is on 32 - bits ;** divising yn by 65536 mean only taking the upper 16 - bits mov datah,macres3 mov datal,macres2 lcall sendltc1452 mov p3,#00 ret ; ---------------------------------------------------- ;* fir filter coefficients table * ; ---------------------------------------------------- ;fsample 480hz, n=16, low pass 0.1hz - 78db @ 60hz coeftable: dw 023dh dw 049dh dw 086ah dw 0d2dh dw 1263h dw 1752h dw 1b30h dw 1d51h dw 1d51h dw 1b30h dw 1752h dw 1263h dw 0d2dh dw 086ah dw 049dh dw 023dh dw 0ffffh ;end of table
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 24 of 80 vmx51c1020 timers the vmx51c1020 includes 3 general - purpose timer/counters o tim er0 o timer1 o timer2 timer0 and timer1 are general purpose timers that can operate as a timer with a clock rate based on the system clock, or as an event counter that monito s r events occurring on an external timer input pin ( t0in for timer 0 and t1in for tim er 1 ) . timers 0 and timer 1 are similar to the standard 8051 timers. apart from also being capabile of operating as a timer based on a system clock or as an event counter, timer2 is also the heart of the pwm counter outputs and the compare and capture u nits. each of the vmx51c1020 ?s timers has a dedicated interrupt vector which can be trigge re d when the timer s overflow. timer 0 and timer 1 the vmx51c1020 ?s timer0 and timer1 are very similar in their structure and operation. the main difference being that timer1 serves as a baud rate generator for uart0 and it shares some of its resources when timer0 is used in mode 3. timer0 and timer1 each consist of a 16 - bit register for which the content is accessible as two independent sfr registers: tlx and thx. t able 39: (tl0) t imer 0 l ow b yte - sfr 8a h 7 6 5 4 3 2 1 0 tl0 [7:0] t able 40: (th0) t imer 0 h igh b yte - sfr 8c h 7 6 5 4 3 2 1 0 th0 [7:0] t able 41: (tl1) t imer 1 l ow b yte - sfr 8b h 7 6 5 4 3 2 1 0 tl1 [7:0] t able 42: (th1) t imer 1 h igh b yte - sfr 8d h 7 6 5 4 3 2 1 0 th1 [7:0] with the exception of their associated interrupt s , the configuration and control of timer0 and timer1 is performed via the tmod and tcon sf r registers. the following table shows the tcon special function register of the vmx51c1020 . this register contains the timer 0/1 overflow flags, timer 0/1 run control bits , interrupt 0/1 edge flags , and the interrupt 0/1 interrupt type control bits. t ab le 43: (tcon) t imer 0, t imer 1 t imer /c ounter control - sfr 88 h 7 6 5 4 tf1 tr1 tf0 tr0 3 2 1 0 ie1 it1 ie0 it0 bit mnemonic function 7 tf1 timer 1 overflow flag. set by hardware when timer 1 overflows. it is automatically cleared when the timer 1 interrupt is serviced. this flag can also be cleared by software. 6 tr1 timer 1 run control bit. tr1 = 0, stop timer 1 tr1 = 1, start timer 1 5 tf0 timer 0 overflow flag. set by hardware when timer 0 overflows. it is automatically c leared when the timer 0 interrupt is serviced. this flag can also be cleared by software. 4 tr0 timer 0 run control bit. tr0 = 0, stop timer 0 tr0 = 1, start timer 0 3 ie1 interrupt 1 edge flag. this flag is set by hardware when falling edge on exte rnal int1 is observed. it is cleared when interrupt is processed. 2 it1 int1 interrupt event type control bit. it1 = 0, interrupt will be caused by a low level on int1 it1 = 1, interrupt will be caused by a high to low transition on int1. 1 ie0 int0 edge flag configuration set by hardware when falling edge on external pin int0 is observed. it is cleared when interrupt is processed. 0 it0 int0 interrupt event type control bit. it0 = 0, interrupt will be caused by a low level on int0 it0 = 1, inte rrupt will be caused by a high to low transition on int0.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 25 of 80 the tmod register is mainly used to set the operating mode of the timers and it allows the user to enable the external gate control as well as select timer or counter operation. t able 44: (tmod) t imer m ode c ontrol - sfr 89 h 7 6 5 4 gate1 ct1 m11 m01 3 2 1 0 gate0 ct0 m10 m00 bit mnemonic function 7 gate1 gate1 = 0, the level present on the int1 pin has no effect on timer1 operation. gate1 = 1, the level of int1 pin serves as a gate control on to timer/counter operation provided the tr1 bit is set. applying a low level on the int1 pin makes the timer stop. ct1 selects timer1 operation. ct1 = 0, sets the timer 1 as a timer which value is incremented by sysclk eve nts. ct1 = 1, the timer 1 operates as a counter which counts the high to low transition on that occurs on the t1in input. 5 m11 4 m01 selects mode for timer/counter 1, as shown in the table below. 3 gate0 gate0 = 0, the level present on the int0 pin has no effect on timer1 operation. gate0 = 1, the level of int0 pin serves as a gate control on to timer/counter operation provided the tr0 bit is set. applying a low level on the int0 pin makes the timer stop. 2 ct0 selects timer 0 operation. ct 1 = 0, sets the timer 0 as a timer which value is incremented by sysclk events. ct1 = 1, the timer 0 operates as a counter which counts the high to low transition on that occurs on the t1in input. 1 m10 0 m00 selects mode for timer/counter 0, as shown in the table below. timer0/timer1/counter operation the ct0 and ct1 bits of the tmod register control the clock source for timer0 and timer1 , respectively. when the ct bit is set to 0 (timer mode) the timer is sourced from the system clock div ided by 12. setting the ctx bit to 1 sets the timer to operate in event counter mode. in this mode , high to low transitions on the txin pin of the vmx51c1020 increments the timer value. note that w hen timer0 and timer1 operate in timer mode, they use th e system clock as th eir source. therefore configuring the clkdivctrl register will affect the timer ? s operation. timer0 & timer1 gate control the gate control makes it possible for an external device to control timer0 and timer1 operation through the inte rrupt (intx) pins. when the gatex and trx bits of the tmod register are set to 1: o intx = logic low, the timer x stops o intx = logic high, the timer x runs when the gate bit equals 0, then the logic level present at the intx pin have no effect on the time r operation. f igure 15: t imer 0, t imer 1 ct x & g ate control sysclk 12 txin ctx=0 ctx=1 trx gatex intx 0 1 clk
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 26 of 80 timer0, timer1 operation modes the operating mode of timer0 and timer1 is determined by the m1x and m0x bits in the tmod register. the following summarizes the fou r modes of operation for timers0 and 1. t able 45: t imer /c ounter m ode d escription s ummary m1 m0 mode function 0 0 mode 0 13 - bit timer / counter , with 5 lower bits in tl0 or tl1 register and bits in th0 or th1 register (for timer 0 an d timer 1, respectively). the 3 high order bits of tl0 and tl1 are held at 0. 0 1 mode 1 16 - bit timer / counter 1 0 mode 2 8 - bit auto reload timer / counter . the reload value is kept in th0 or th1, while tl0 or tl1 is incremented every machine cycle. wh en tlx overflows, a value from thx is copied to tlx. 1 1 mode 3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independent 8 - bit timers / counters. mode 0, 13 - bit timer/counter mode 0 o peration is the same for timer0 and timer1. in mode 0, the timer is configured as a 13 - bit counter that uses bits 0 - 4 of the tlx register and all 8 - bits of the thx register. the timer run bit (trx) of the tcon sfr starts the timer. the value of the ctx b it defines if the timer will operate as a timer (ctx = 0) , deriving its source from the system clock , or count the high to low transitions (ctx = 1) that occurs on the external timer input pin (txin). when the 13 - bit count increments from 1fffh (all ones) to all zeros , the tf0 (or tf1) bit will be set in the tcon sfr . the state of the upper 3 - bits of the tlx register is indeterminate in mode 0 and must be masked when the software evaluates the register?s content s . timer 0, timer 1: mode 0 - overflow r ate (hz) ctx = 0 timer overflow rate (hz) = f sysclk _________ 12 x [8192 - (thx, tlx)] ctx = 1 timer overflow rate (hz) = f txin _________ [8192 - (thx,tlx)] mode 1 (16 - bit) mode 1 operation is the same for timer0 and timer1. in mode 1, the timer is configured as a 16 - bit counter. other than rollover at ffffh, mode 1 operation is the same as mode 0. f igure 16 : t imer 0 m ode 0 & m ode 1 sysclk 12 p3.2-t0in ct0=0 ct0=1 tr0 gate0 int0 0 1 0 7 4 mode = 0 0 7 th0 tf0 int tl0 clk mode = 1 f igure 17: t imer 1 m ode 0 & m ode 1 sysclk 12 p3.5-t1in ct1=0 ct1=1 tr1 gate1 int1 0 1 0 7 4 mode = 0 th1 clk mode = 1 0 7 tf1 int tl1 to uart0 the timer0 and timer1 overflow rate in mode 1 can be calculated using the following equations: timer 0, timer 1: mode 1 - overflow rate (hz) ctx = 0 timer overflow rate (hz) = f sysclk _________ 12 x [65536 - (thx, tlx)] ctx = 1 timer overflow rate (hz) = f txin _________ [65536 - (thx, tlx)] mode 2 (8 - bit) the operation of mode2 is the same for timer0 and timer1. in mode 2, the timer is configured
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 27 of 80 as an 8 - bit counter, with automatic reload of the start value. the lsb of the timer register, tlx , is the counter itself and the msb portion of the timer, thx, stores the timer reload value. mode 2 ?s counter control is the same as for mode 0 and mode 1. however, in mode 2, when tlx rolls over from ffh, the value stored in thx is reloaded into tlx. f igure 18 : t imer 0 m ode 2 12 p3.2 - t0in ct0 = 0 ct0 = 1 tr0 gate0 0 1 0 7 th0 sysclk tf0 int 0 7 int0 tl0 f igure 19: t imer 1 m ode 2 12 p3.5 - t1in ct1 = 0 ct1 = 1 tr1 gate1 0 1 0 7 th1 sysclk tf1 to uart0 int 0 7 int1 tl1 the timer0 and timer1 overflow rate in mode 2 can be calculated using the following equations: timer 0, timer 1: mode 2 - overflow rate (hz) ctx = 0 timer overflow rate (hz) = f sysclk _________ 12 x [256 - (thx)] ctx = 1 timer overflow rate (hz) = __ f txin ________ [256 -- (thx)] using timer1 as baud rate generator using timer1 in mode 2 is recommended as the best approach when using timer1 as the uart0 baud rate generator. mode 3 (2 x 8 - bit) in mode 3, timer0 operates as two 8 - bit counters and timer1 stops counting and holds its value. f ig ure 20: t imer 0, t imer 1 structure in m ode 3 sysclk 12 p3.2-t0in ct0 = 0 ct0 = 1 tr0 gate0 int0 0 1 tr1 0 7 th0 clk 0 7 tl0 clk tf0 tf1 int int to uart0 the timer0 overflow rate in mode 3 can be calculated by using following equations: timer 0, timer 1: mode 3 - overflow rate (hz) th0, ctx = 0 or 1 timer overflow rate (hz) = f sysclk _____ 12 x 256 tl0, ctx = 0 timer overflow rate (hz) = f sysclk _____ 12 x 256 tl0, ctx = 1 timer overfl ow rate (hz) = __ f txin _____ 256 in mode 3, the values present in the th1 and tl1 registers , as well as the value of the gate1 and ct1 control bits , have no impact on the timer operat ion . timer0 & timer1 interrupts timer0 and timer1 have a dedicated interrupt v ector s located at: o 000bh for the timer 0 o 001bh for the timer 1 the natural priority of timer0 is higher than th at of timer1.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 28 of 80 the following table provid es a summary of the int errupt control and flag bit s associated with the timer0 and timer1 interrupts. bit name location description ea ien0.7 general interrupt control bit 0, interrupt disabled 1, enabled interrupt active t0ie ien0.1 timer 0 overflow interrupt 1 = enable 0 = disable t1ie ien0.3 timer 1 overflow interrupt 1 = enable 0 = disable tf0 tcon.5 tf0 flag is set when timer 0 overflow occurs. automatically cleared when timer 0 interrupt is serviced. this flag can also be cleared by software tf1 tcon.7 tf1 flag is set when timer 1 overflow occurs. automatically cleared when timer 1 interrupt is serviced. this flag can also be cleared by software setting up timer0 example in order to use timer0, the first step is to setup the interrupt and then configure the module a nd this is described in the following code example . sample c code to set up timer 0: // --------------------------------------------------------------------------- // sample c code to setup timer 0 // ------------------------------------------------------- -------------------- // (?) program initializat ion omitted at 0 x 0100 void main ( void ){ // i nterrupt + timer 0 setup ien0 |= 0 x 80; // e nable all interrupts ien0 |= 0 x 02; // e nable interrupt t imer 0 tmod = 0 x 02; // t imer 0 m ode 2 tcon = 0 x 10; // s tart t imer 0 do {} while (1); // wait for timer 0 interrupt }// end of main () // --------------------------------------------------------------------------- // i nterrupt function void int _ timer _0 ( void ) i nterrupt 1 { ien0 &= 0 x 7f; // d isable all interrupt s /* ------------------------ */ /*put interrupt code here*/ /* ------------------------ */ ien0 |= 0x80; // enable all interrupts } // --------------------------------------------------------------------------- setting up timer1 example the following code p rovides an example of how to configure timer1 ( first part of the code is the interrupt setup and module configuration whereas the second part is the interrupt function ) . example1: delay function // ------------------------------------------------------- ------------------ // sample c code using the timer 1: delay function // ------------------------------------------------------------------------- void delay 1 ms ( unsigned char dlais ) { idata unsigned char x =0; tmod = 0 x 10; tl1 = 0 x 33; th1 = 0 x fb; ;/ / timer 1 reload value for tcon = 0 x 40; while ( dlais > 0) { do { x =tcon; x = x &0 x 80; } while ( x ==0); tcon = tcon&0 x 7f; tl1 = 0 x 33; th1 = 0 x fb; ;// timer 1 reload value for dlais = dlais - 1; } }// end of delay 1 ms example 2: t imer 1 interrupt example // ------------------------------------------------------------------------- // sample c code using the timer 1: interrupt // ------------------------------------------------------------------------- // (?) program initializat ion omitted at 0xo100 void main(void){ // timer 1 setup ien0 |= 0x80; // enable all interrupts ien0 |= 0x08; // enable interrupt timer1 tmod = 0x20; // timer 1 mode 2 tcon = 0x40; // start timer 1 tl1 = 0xfc; // timer1 offset do { }while(1); //wait timer 1 interrupt }//end of main() function // ---------------------------------------- // timer 1 interrupt function // ---------------------------------------- void int_timer_1 (void) interrupt 3 { ien0 &= 0x7f; // disable all interrupts /* put interrupt code here*/ ien0 |= 0x80; // enable all interrupts }
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 29 of 80 timer 2 the vmx51c1020 timer2 and associated peripherals include the following capabilities : o 16 - bit timer o 16 - bit auto - reload timer o compare and capture units o 8 / 16 pwm outputs t able 46: (tl2) t imer 2, l ow b yte - sfr cc h 7 6 5 4 3 2 1 0 tl2 [7:0] t able 47: (th2) t imer 2, h igh b yte - sfr cd h 7 6 5 4 3 2 1 0 th2 [7:0] figure 21 shows the timer2 compare/capture unit block diagram. the following p aragraphs will describe describe how these blocks work. t imer2 registers timer2 consti s ts of a 16 - bit register, wh ose upper and lower bytes are accessible via two independent sfr registers (tl2, th2). t able 48: (tl2) t imer 2 l ow b yte - sfr cc h 7 6 5 4 3 2 1 0 tl2 [7:0] t able 49: (th2) t imer 2 h igh b yte - sfr cd h 7 6 5 4 3 2 1 0 th2 [7:0] timer2 control register most of timer2 ?s control is accomplished via the t2con register located at sfr address c8h. the t 2con register controls: o t2 clock source prescaler o t2 count size (8/16 - bits) o t2 reload mode o t2 input selection t able 50: (t2con) t imer 2 c ontrol r egister - sfr c8 h 7 6 5 4 t2ps t2psm t2size t2rm1 3 2 1 0 t2rm0 t2cm t2in1 t2in0 bit mnemonic function 7 t2ps prescaler select bit: 0 = timer 2 is clocked with 1/12 of the oscillatory frequency 1 = timer 2 is clocked with 1/24 of the oscillatory frequency 6 t2psm 0 = prescaler 1 = clock/2 5 t2size timer 2 size 0 = 16 - bit 1 = 8 - bit 4 t2rm1 3 t2rm0 timer 2 reload mode selection 0x = reload disabled 10 = mode 0 11 = mode 1 2 t2cm timer 2 compare mode selection 0 = mode 0 1 = mode 1 1 t2in1 0 t2in0 timer 2 input selection 00 = timer 2 stops 01 = input frequency f/2, f/12 or f/24 10 = timer 2 is incremented by external signal at pin t2in 11 = internal clock is gated to the t2in input.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 30 of 80 f igure 21: t imer 2 and c ompare /c apture unit t2exie sysclk interrupt request input/output control timer 2 16-bit comparator 16-bit comparator 16-bit comparator 16-bit comparator tl2 th2 t2if sync t2exif reload sync t2ex t2in crcl crch ccl1 ccl2 ccl3 cch1 cch2 cch3 data latch data latch data latch data latch capture compare capture compare capture compare capture capture compare capture capture comp capture capture reload compare capture comp capture capture comp capture capture comp capture data latch enable enable enable enable cocah3 cocah3 cocah3 cocah2 cocah2 cocah2 cocah1 cocah1 cocah1 cocah0 cocah0 cocah0 cocah0 t2size 2 12 2 t2psm t2ps t2inxx 00 01 11 10 0 1 0 1 ccu0 ccu1 ccu2 intcomp2 intcomp3 intcomp0 intcomp1 p1.0-pwm0 p1.1-pwm1 p1.2-pwm2 p1.3-pwm3 timer2 clock sources as previously stated, timer2 can op erate in timer mode, in which case it derives its source from the system clock (sysclk) or it can be configured as an event counter where the high to low transition on the t2in input makes the timer 2 to increment. the t2in0 and t2in1 bits of the t2con re gister serve to define the selected timer2 input and the operating mode of timer2 (see following table). t imer 2 c lock source t2in1 t2in0 selected timer 2 input 0 0 timer 2 stop 0 1 standard timer mode using internal clock with or without prescaler 1 0 external t2in pin clock timer2 1 1 internal clock is gated by the t2in input when t2in = 0, the timer2 stop when in timer mode , timer2 derives its source from the system clock and the clkdivctrl register will affect timer 2 ?s operation. timer 2 stop when both t2in1 and t2in0 bit are set to 0 , timer2 is in stop mode. timer2 operating modes when the t2in1 bit is set to 0 and the t2in0 bit is set to 1 , timer2 derives its source from the internal pre - scaled clock or not, depending on the t2psm bit value . event counter mode when operating in the event counter mode, the timer is incremented as soon as the external signal t2in transitions from a 1 to a 0. a sample of the t2in input is taken at every machine cycle. timer 2 is incremented in the cycle foll owing the one in which the transition was detected. gated timer mode in the gated timer mode, the internal clock, which serves as the timer2 clock source, is gated by the external signal t2in. in other words, when t2in is high, the internal clock is allow ed to pass through the and gate. a low value of t2in will diable the clock pulse. this provides the ability for an external device to control timer2 ?s operation or to use timer2 to monitor the duration of an event.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 31 of 80 timer2 clock prescaler when timer2 is configured so that it derives its clock source from the system clock, the clock prescaling value can be controlled by software using the t2psm and the t2ps bit of the t2con register. the different system clock prescaling values are shown in the following table : t2psm t2ps timer 2 input clock 1 x sysclk / 2 0 0 sysclk / 12 0 1 sysclk / 24 timer2 count size timer2 can be configured to operate in 8 - bit or 16 - bit formats. the t2size bit of the t2con register selects the timer2 count size. o if t2size = 0, timer2 size is 16 - bits o if t2size = 1, timer2 size is 8 - bits timer2 reload modes the timer2 reload mode is selected by the t2rm1 and t2rm0 bits of the t2con register. the following figure shows the reload operation. timer2 must be configured as a 16 - bit timer/counter for the reload modes to be operational by clearing the t2size bit. timer 2 mode 0 when the timer overflows, the t2if overflow flag is set. concurrently, this overflow causes timer2 to be reloaded with the 16 - bit value contained in the cr c x register, (which has been preset by software). this reload operation will occur during the same clock cycle in which t2if was set. timer2 mode 1 in mode 1, a 16 - bit reload from the crcx register on the falling edge of t2ex occurs. this transition will set t2exif if t2exie is set. this action will cause an interrupt (providing that the timer2 interrupt is enabled) and the t2if flag value will not be affected. the value of the t2size does not affect the reload in mode 1. also, the reload operation is p erformed independently of the state of the t2exie bit. f igure 22: t imer 2 r eload m ode exf2 t2if timer 2 interrupt request reload mode 1 reload mode 0 t2ex input clock reload data bus data bus tl2 th2 data bus data bus crcl crch t2exie data latch data latch timer2 overflows and interrupts timer2 ?s interrupt is enabled when the timer2 counter, the t2if flag is set, and a timer 2 interrupt occurs . a timer2 interrupt may also be raised from t2ex if the t2exie bit of the ien1 register is set. finding the exact source of a timer2 interrupt can be verified by checking the value of the t2if and the t2exif bits of the ircon register. timer2?s interr upt vector is located at address 002bh
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 32 of 80 timer2 setup example in order to use timer2, one must first set up and configure the module (see following code example) . // --------------------------------------------------------------------------- // sample c cod e to setup timer 2 // --------------------------------------------------------------------------- // (?) program initializat ion omitted at 0x100 void main(void){ // timer 2 & interrupt setup digpwren = 0x80; // enable timer2, t2con = 0x01; // set tim er 2 to osc/12 tl2 = 0xe0; th2 = 0xff; ien0 |= 0x80; // enable all interrupts ien0 |= 0x20; // enable interrupt timer 2 do{ //wait for timer 2 interrupt }while(1); }//end of main() // --------------------------------------------------------------- ------------ // timer 2 interrupt function // --------------------------------------------------------------------------- void int_timer_2 (void) interrupt 5 { ien0 &= 0x7f; // disable all interrupts /* ------------------------ */ /*interrupt code here*/ / * ------------------------ */ ien0 |= 0x80; // enable all interrupts } timer2 special modes for general timing/counting operations, the vmx51c1020 ?s timer2 includes 4 compare and capture units that can be used to monitor specific events and serve to driv e pwm outputs. each compare and capture unit provides three specific operating modes that are controlled by the ccen register . these 3 modes are: o compare modes enable. o capture on write into crcl/cclx registers. o capture on transitions at ccu input pins le vel. t able 51: (ccen) c ompare /c apture e nable r egister - sfr c9 h 7 6 5 4 cocah3 cocal3 cocah2 cocal2 3 2 1 0 cocah1 cocal1 cocah0 cocal0 the ccen register bits are grouped in pairs of cocahx/cocalx bits. each pair corresponds to on e compare and capture unit. the compare and compare unit operating mode vs. the configuration bit is described in the following table. bit mnemonic mnemonic function cocah0 cocal0 compare and capture mode for crc register 0 0 compare/capture disable d 0 1 capture on a falling edge at pin ccu0 (1 cycle) 1 0 compare enabled (pwm0) 1 1 capture on write operation into register crc1 cocah1 cocal1 compare/capture mode for cc register 1 0 0 compare/capture disabled 0 1 capture on a rising edge at pin ccu1 (2 cycles) 1 0 compare enabled (pwm1) 1 1 capture on write operation into register ccl1 cocah2 cocal2 compare/capture mode for cc register 2 0 0 compare/capture disabled 0 1 capture on a rising edge at pin ccu2 (2 cycles) 1 0 compare enabled (p wm2) 1 1 capture on write operation into register ccl2 cocah3 cocal3 compare/capture mode for cc register 3 0 0 compare/capture disabled 0 1 n/a - ccu3 not pinned out 1 0 compare enabled (pwm) 1 1 capture on write operation into register ccl3 thi s allows individual configur ation and operation of each compare and capture unit . compare/capture & reload registers each compare and capture unit has a specific 16 - bit register accessible via two sfr addresses. note that the crchx/crclx registers assoc iated with compare/capture unit 0 are the only ones that can be used to perform a reload of timer2 operation. the following tables describe the different registers that may be capture d or compared to the value of timer2. t able 52: ( crcl) c ompare /r eload /c apture r egister , l ow b yte - sfr ca h 7 6 5 4 3 2 1 0 crcl [7:0] t able 53: (crch) c ompare /r eload /c apture r egister , h igh b yte - sfr cb h 7 6 5 4 3 2 1 0 crch [7:0]
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 33 of 80 t able 54: (ccl1) c ompare /c a pture r egister 1, l ow b yte - sfr c2 h 7 6 5 4 3 2 1 0 ccl1 [7:0] t able 55: (cch1) c ompare /c apture r egister 1, h igh b yte - sfr c3 h 7 6 5 4 3 2 1 0 cch1 [7:0] t able 56: (ccl2) c ompare /c apture r egister 2, l ow b yte - sfr c4 h 7 6 5 4 3 2 1 0 ccl2 [7:0] t able 57: (cch2) c ompare /c apture r egister 2, h igh b yte - sfr c5 h 7 6 5 4 3 2 1 0 cch2 [7:0] t able 58: (ccl3) c ompare /c apture r egister 3, l ow b yte - sfr c6 h 7 6 5 4 3 2 1 0 ccl3 [7:0] t able 59: (cch3) c ompare /c apture r egister 3, h igh b yte - sfr c7 h 7 6 5 4 3 2 1 0 cch3 [7:0] compare/capture data line width the vmx51c1020 is capable of comparing and capturing data using data lines up to 16 bits wide. when comparing 2 registers or capturing 1 register, it is required to set the t2size bit of the t2con register to 1. this adjusts the line width to 8 - bit s . w hen comparing two pairs of registers, for example , cch1 and ccl1 to th2 and tl2, the t2size bit must be set to 0. this adjusts the line width to 16 bits. timer2 capture modes the timer2 capture modes allow acquir ing and stor ing the 16 - bit content s of timer2 into a capture/compare register following a mov sfr operation or the occurrence of an extern al event on one of the ccu pin s (described in the following table). capture input timer 2 capture triggering event ccu0 high to low transition on ccu0 ccu1 low to high transition on ccu1 ccu2 low to high transition on ccu2 timer2 capture is done with out affecting timer2 operation. each individual compare and capture unit can be configured for capture mode by configuring the appropriate bit pair of the ccen register. the two capture modes are mode 0 and mode 1. capture mode 0 in capture mode 0, a tran sition on a given ccu pin triggers the latching of timer2 data in to the associated compare/capture register. capture mode 1 in capture mode 1, a capture of the timer2 value will occur upon writing to the low byte of the chosen capture register. note: o n the vmx51c1020 , the ccu3 input is not pinned out. f igure 23: t imer 2 c apture m ode 0 for crcl and crch b lock d iagram input clock reload data bus data bus tl2 th2 data bus data bus crcl / cclx crch / cchx data latch data latch write to crcl, cclx timer 2 interrupt request capture mode 1 capture mode 0 ccux pin t2if the capture modes can be especially useful for external event duration calculation with the ability to latc h the timer value at a given time ( computation can then be performed at a later time ) . when operating in capture modes, the compare and capture units don?t affect the vmx51c1020 interrupts. timer2 compare modes in compare mode, a timer2 count value is co mpared to a value that is stored in the cchxx/cclx or crchx/crclx registers. if the values compared match (i.e. when the pulse changes state), a compare/capture interrupt is generated, if enabled. varying the value of the cchx/cclx or crchx/crclx allows a variation of the rectangular pulse generated at the output. this variation can be used to perform pulse width modulation. see pwm i n the following section. in order to activate the compare mode on one of the four compare capture units, the associated coc ahx and cocalx bit s must be set to 1 and 0, respectively
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 34 of 80 when the compare mode is enabled, the corresponding output pin value is under the control of the internal timer circuitry. on the vmx51c1020 , two compare modes are possible. in both modes, the n ew value arrives at port pin 1 in the same clock cycle as the internal compare signal is activated. the t2cm of the t2con register defines the compare mode and is described in the following paragraphs. compare mode 0 a functional diagram of compare mode 0 is shown below. a comparison is made between the 16 - bit value of the compare/capture registers and the th2, tl2 register s . when the timer2 value exceeds the value stored in the crch, crcl / cchx, cclx registers, a high compare signal is generated and a compare/capture interrupt is activated if enabled. if t2size = 1, the comparison is made between the tl2 and crcl/cclx register. this compare signal is then propagated to the pin corresponding p1.x pin(s) and to th e associated compintx interrupt (if e nabled). the corresponding p1.x pin is reset when a timer2 overflow occurs. f igure 24: t imer 2 c ompare m ode 0 b lock d iagram comparator th2 tl2 timer 2 crch, cchx crcl, cclx overflow timer 2 interrupt reset register compare signal p1.0- pwm0 set register p1.1- pwm1 p1.2- pwm0 p1.3- pwm0 compxint interrupt compare mode 1 when a given compare capture unit is operating in mode 1, any write operations to the corresponding output register of the port p1.x (x=0 to3) will not appear on the physical port pin until the next compare match occurs. as is the case in compare mode 0, the compare signal in mode 1 can also generate an interrupt (if enabled). the figur e below shows the operating structure of a given capture compare unit operating in compare mode 1. f igure 25: t imer 2 c ompare m ode 1 b lock d iagram comparator th2 tl2 timer 2 crch, cchx crcl, cclx overflow timer 2 interrupt compare signal p1.0- pwm0 data latch shadow register output register port register circuit compxint interrupt p1.1- pwm1 p1.2- pwm2 p1.3- pwm3 timer 2 compare mode interrupt c onfiguration of the compare and capture units for the ?compare mode? through the ccen register has an impact on the interrupt structure of the vmx51c1020 . in that specific mode each compare capture unit take s control of one interrupt line. when using the pwm output device, some care must be excer cised to avoid other peripheral interrupt s from being blocked by this mechanism.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 35 of 80 f igure 26: c ompare and c apture u nit i nterrupt control compint0 interrupt 0 1 interrupt vector 0053h spi rx & rxov int ccen(1,0) = 1,0 compint1 interrupt 0 1 interrupt vector 005bh i2c int ccen(3,2) = 1,0 compint2 interrupt 0 1 interrupt vector 0063h mac overflow int ccen(5,4) = 1,0 compint3 interrupt 0 1 interrupt vector 006bh adc & port change int ccen(7,6) = 1,0 using timer 2 for pwm outputs configuring the compare and capture units in com pare mode 0 allows pwm output generation on the port1 i/o pins . this mode can be used for pwm applications such as: o d/a conversion o motor control o light control o etc. when one specific compare and capture unit is configured for this mode, its associated i /o pin is reserved for this operation only and any write operation to the associated i/o pin of the p1 register will have no effect on it. the following table shows the association between the compare and capture units, associated registers and i/o pin t able 60: c ompare and c apture u nit pwm association compare capture unit registers i/o pin 0 crch / crcl p1.0 1 cch1 / ccl1 p1.1 2 cch2 / ccl2 p1.2 3 cch3 / ccl3 p1.3 pwm signal generation is derived from the comparison result betwe en the values stored into the capture compare registers and the timer2 value. when a digital value is written into one of the compare and capture registers, a comparison is performed between this register and the timer2 value (providing that timer2 is in compare mode). as long as the value present in the compare and capture register is greater than the timer2 value, the compare unit will output a logic low. when the value of timer2 equals the value of the compare and capture register, the compare unit wi ll change from a logic low to a logic high. the clock source for the pwm is derived from timer2 ; which is incremented at every signal pulse of the appropriate source. the source is selected by the t2in1 and t2in0 bits of the t2con register the t2size bit of the t2con register allows configuring the pwm output for 8 or 16 - bit operation . the timer2 size affects all the pwm outputs. when the timer2 size is 8 - bits, the comparison is performed between timer2 and the lsb of the compare and capture unit regist er. the resulting pwm resolution is 8 - bit. when the timer2 size is configured for 16 - bit operation, the comparison is performed between timer2 and the content s of the whole compare and capture unit register. the resulting pwm resolution is 16 - bit s but the pwm frequency is consequently low. when the system clock is used as the timer2 clock source, the pwm output frequency equals the timer2 overflow rate. note that the clkdivctrl register content s affect s timer2 operation and thus, pwm output frequency. f osc t2con t2psm t2con t2ps t2con t2size freq pwm 1 x 0 112.5hz 1 x 1 28.8khz 0 0 - 12 1 - 8 4.8khz 0 0 - 12 0 - 16 18.8hz 0 1 - 24 1 - 8 2.4khz 14.74mhz 0 1 - 24 0 - 16 9.38hz the duty cycle of the pwm output is proportional to the ratio of the compare and ca pture unit register?s content v ersu s the maximum timer2 number of cycles before overflow: 256 or 65536 , depending on the t2size bit value
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 36 of 80 pwm duty cycle calculation: 8 - bit pwm duty cycle ccu0 (%) = 100% x (256 - crcl)_ 256 pwm duty cycle ccu1 - 3 (%) = 100% x (256 - cclx)_ 256 pwm duty cycle calculation: 16 - bit pwm duty cycle ccu0 ( %) = 100% x 65536 ? (crch, crcl) (crch, crcl) pwm duty cycle ccu1 - 3 (%) = 100% x 65536 ? (crch, crcl) (crch, crcl) p wm configuration example the following example shows how to configure the timer2 based pwm in 8 - bit mode. (?) digpwren = 0x80; //enable timer 2 module t2con = 0x61; //bit 7 - select 0=1/12, 1=1/24 of fosc //bit 6 - t2 clk source: 0 = presc, 1=clk/2 //bit 5 - t2 size: 0=16 - bit, 1=8 - bit //bit 4,3 - t2 reload mode: //bit 2 - t2 compare mode //bit 1,0 - t2 input select: 01= input derived from osc. //w hen the pwm is configured in 16 - bit format , the pwm output frequency is given b y // the following expres sion : // pwm freq = [(fosc/2)] / 65536 // w ith a 14.7456mh z c rystal pwm frequency = 112.5h z //when the pwm is configured in 8 - bit its output freq = [(fosc/2)] / 256 //u sing a 14.7456mh z c rystal pwm frequency = 28.8 k h z ccen = 0x0 aa; //enable compare on 4 pwm outputs // in 16 - bit pwm resolution both lsb and msb of compare unit are used //in 8 - bit pwm resolution, only the lsb of compare units are used // and msb is kept to 00h crcl = 0x0e6; //pwm0 duty = [(256 - crcl)/256] x100 % crch = 0x000; //e6h => 10.1% ccl1 = 0x0c0; //pwm1 duty = [(256 - ccl1)/256] x100% cch1 = 0x000; //c0h => 25% ccl2 = 0x080; //pwm2 duty = [(256 - ccl2)/256] x100% cch2 = 0x000; //80h => 50% ccl3 = 0x033; //pwm3 duty = [(256 - ccl3)/256] x100% cch3 = 0x000; //33h => 80% p1pincfg = 0x0f; //configure p1 lsq as output to enable pwm (?) using the pwm as a d/a converter one of the popular uses of the pwm is to perform d/a conversion by low pass filtering its? modulated square wave output. the greater the duty cycle of the square wave, the greater the dc value is at the output of the low pass filter and vice versa. v ariation s in the duty cycle of the pwm when filtered can therefore generate arbitrary waveforms.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 37 of 80 serial uart interfaces the vmx51c1020 includes two serial uart interface ports ( uart0 and uart1 ) . each serial port has a 10 - bit timer devoted to baud rate generation. both serial ports can operate in full duplex mode. the vmx51c1020 also includes a double buffer , enabling the uar t to accept an incoming word before the software has read the previous value. uart0 serial interface the operation of uart0 of the vmx51c1020 is similar to the standard 8051 uart. uart0 can derive its clock source from a 10 - bit dedicated baud rate generator or from the timer1 overflow. uart0 ?s transmit and receive buffers are accessed through a unique sfr register named s0buf. the uart0 s0buf has a double buffering feature on reception which allows accepting an incoming word before the software h as read the previous value from the s0buf. t able 61: (s0buf) s erial p ort 0, d ata b uffer - sfr 99 h 7 6 5 4 3 2 1 0 s0buf [7:0] uart0 control register uart0 configuration is performed mostly via the s0con sfr register located at address 98h. t able 62: (s0con) s erial p ort 0, c ontrol r egister - sfr 98 h 7 6 5 4 s0m0 s0m1 mpce0 r0en 3 2 1 0 t0b8 r0b8 t0i r0i bit mnemonic function 7 s0m0 6 s0m1 sets serial port operating mode see table 5 mpce 1 = enables the multiprocessor communication feature. 4 r0en 1 = enables serial reception. cleared by software to disable reception. 3 t0b8 the 9 th transmitted data bit in modes 2 and 3. set or cleared by the cpu, depending on the function it performs (parity check , multiprocessor communication etc.) 2 r0b8 in modes 2 and 3, it is the 9 th data bit received. in mode 1, if sm20 is 0, rb80 is the stop bit. in mode 0, this bit is not used. must be cleared by software. 1 t0i transmit interrupt flag set by hardware afte r completion of a serial reception. must be cleared by software. 0 r0i receive interrupt flag set by hardware after completion of a serial reception. must be cleared by software. uart0 operating modes uart0 can operate in four distinct modes, which are defined by the sm0 and sm1 bits of the s0con register (see following table). t able 63: s erial p ort 0 modes sm0 sm1 mode description baud rate 0 0 0 shift register fosc/12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart fclk/32 or /64 1 1 3 9 - bit uart variable ** note that the speed in mode 2 depends on smod bit in the special function register pcon when smod = 1 fclk/32
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 38 of 80 uart0 - mode 0 in this mode, pin rx0 is used as an input and an output, while tx0 is used only to output the shift c lock. for an operation in this mode, 8 bits are transmitted with the lsb as the first bit. additionally , the baud rate is fixed at 1/12 of the crystal oscillator frequency. in order to initialize reception in this mode, the user must set bits r0i and r0en in the s0con register to 0 and 1 , respectively. note that in other modes, when r0en=1, the interface begins to receive data. uart0 - mode 1 in this mode, the rx0 pin serves as an input and the tx0 pin as a serial output and no external shift clock is use d. in mode 0, 10 - bits are transmitted: o s tart bit (logic low) ; o 8 - bits of data ( lsb first) ; o a stop bit (logic high) . t he start bit synchronizes data reception, with the 8 - bits of received data then being available in the s0buf register . r eception is comp leted once the stop bit sets the r0b8 flag in the s0con register. uart0 - mode 2 in this mode the rx0 pin is used as an input and an output while tx0 is used to output the shift clock. in mode 2 , 11 bits are transmitted / received. hese 11 - bits consist of : o s tart bit (logic low) o 8 bits of data (lsb first), o one programmable 9 th bit, o s top bit (logic high) . t he 9 th bit is used for parity . in the data transmission case , bit tb80 of the s0con is output as the 9 th bit. for reception, the 9 th bit will be s tored captured in the rb80 bit of the s0con register. uart0 - mode 3 mode 3 is essentially identical to mode 2 , with the difference being that the internal baud rate generator or timer 1 can be used to set the baud rate. uart0 - baud rate generator sour ce as mentioned previously , the uart0 baud rate clock can be sourced from either timer 1 or the dedicated 10 - bit baud rate generator . s election between these sources is enabled via the baudsrc bit of the u0baud register (see following table). t able 64: (u0baud) uart0 b aud rate source sele ct - sfr d8 h 7 6 5 4 3 2 1 0 baudsrc - - - - - - - 7 baudsrc baud rate generator clock source 0 = timer 1 1 = use uart0 dedicated baud rate generator 6:0 - -
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 39 of 80 u s ing the uart0 dedicated baud rat e generator , f ree s up timer 1 for other uses . the s0relh and s0rel registers are used to stor e the 10 - bit reload value of the uart0 baud rate generator. t able 65: (s0rell) s erial p ort 0, r eload r egister , l ow b yte - sfr 96 h 7 6 5 4 3 2 1 0 s0rell [7:0] t able 66: (s0relh) s erial p ort 0, r eload r egister , h igh b yte - sfr 97 h 7 6 5 4 3 2 1 0 s0relh [15:8] the following equations should be used to calculate the reload value for the sorel register (examples follow). mode 3: for baudsrc=1 sorel = 1024 ? 2 smod x f clk_______ 64 x baud rate baud rate = 2 smod x f clk____ 64 x (1024 ? s0rel) t able 67: s eri al 0 b aud r ate s ample v alues baudsrc = 1, smod = 1 desired baud rate s0rel @ f clk = 11.059 mhz s0rel @ f clk = 14.75 mhz 500.0 kbps - - 460.8 kbps - 3ffh 230.4 kbps - 3feh 115.2 kbps 3fdh 3fch 57.6 kbps 3fah 3f8h 19.2 kbps 3eeh 3e8h 9.6 kbps 3dch 3d 0h 2.4 kbps 370h 340h 1.2 kbps 2e0h 280h 300 bps - - t able 68: s erial 0 b aud r ate s ample v alues baudsrc =1, smod = 0 desired baud rate s0rel @ f clk = 11.059 mhz s0rel @ f clk = 14.75 mhz 115.2 kbps - 3feh 57.6 kbps 3fdh 3fch 19. 2 kbps 3f7h 3f4h 9.6 kbps 3eeh 3e8h 2.4 kbps 3b8h 3a0h 1.2 kbps 370h 340h 300 bps 1c0h 100 timer1 can also be used as the baud rate generator for the uart0. set baudsrc to 0 and assign timer 1?s output to uart0. when the baud rate clock sourc e is derived from timer1, the baud rate and timer reload value s can be calculated using the following formulas (examples follow). t able 69: e quation to calculate b aud r ate for s erial 0 serial 0: mode 1 and 3 mode 1: foru0baud.7=0 (st andard mode) baud rate = 2 smod x f clk _ 32 x 12 x (256 - th1) th1 = 256 - 2 smod x f clk____ 32x12x baud rate t able 70: uart 0 b au d r ate s ample v alues baudsrc =0, smod = 1 desired baud rate th1 @ f clk = 11.059 mhz th1 @ f clk = 14.75 mhz 115.2 kbps - - 57.6 kbps ffh - 19.2 kbps fdh fch 9.6 kbps fah f8h 2.4 kbps e8h e0h 1.2 kbps d0h c0h 300 bps 40h - t able 71: uart 0 b aud r ate s ample v alues baudsrc =0, smod = 0 desired baud rate th1 @ f clk = 11.059 mhz th1 @ f clk = 14.75 mhz 115.2 kbps - - 57.6 kbps - - 19.2 kbps - feh 9.6 kbps fdh fch 2.4 kbps f4h f0h 1.2 kbps e8h e0h 300 bps a0h 80h
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 40 of 80 example of uart0 setup and use in order to use uart0, the following operations must be performed: o enable the uart0 interface o set i/o pad direction tx= output, rx=input o enable reception (if required) o configure the uart0 controller s0con the following are configurati on and transmission code examples for uart0. // ---------------------------------------------------------------------------------------- // // uart0 config with s0rel // // configure the uart0 to operate in rs232 mode at 19200bps // with a crystal of 14.745 6mhz // // ---------------------------------------------------------------------------------------- // void uart0ws0relcfg() { p3pincfg |= 0x01; // pads for uart 0 digpwren |= 0x01; // enable uart0/timer1 s0rell = 0xf4; //com speed = 19200bps s0relh = 0x03; s0con = 0x50; // uart0 in mode1, 8 bit, var. baud rate u0baud = 0x80; //set s0rel is source for uart0 //baud rate clock }//end of uart0ws0relcfg() function // -------------------------------------------------------------------------------- -------- // // uart0 config with timer 1 // // configure the uart0 to operate in rs232 mode at 19200bps // with a crystal of 14.7456mhz // // ---------------------------------------------------------------------------------------- // void uart0wtimer1cfg() { p3pincfg |= 0x01; // pads for uart0 digpwren |= 0x01; // enable uart0/timer1 tmod &= 0x0f; tmod =0x20; //set timer 1, gate 0, mode 2 th1 = 0xfe; //com speed = 19200bps tcon &= 0x0f; tcon =0x40; //start timer 1 u0baud = 0x00; //set timer 1 b aud rate //generator for uart0 pcon = 0x00; //set smod = 0 s0con = 0x50; // config uart0 in mode 1, //8 bit, variable baud rate }//end of uart1config() function // ----------------------------------------------------------------------------------- ----- // // txmit0() // // one byte transmission on uart0 // ---------------------------------------------------------------------------------------- // // - constants definition sbit uart_tx_empty = userflags^1; void txmit0( unsigned char charact){ s0buf = charact; userflags = s0con; //wait tx empty flag to be raised while (!uart_tx_empty) {userflags = s0con;} s0con = //clear both r0i & t0i bits s0con & 0xfd; }//end of txmit0() function see the interrupt section for example of setup of uart0 interr upts
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 41 of 80 uart1 serial interface the uart1 serial interface is based on a subset of uart0. it provides two operating modes and its clock source is derived exclusively from a dedicated 10 - bit baud rate generator. the uart1 transmit and receive buffers are a ccessed via sfr register s1buf. t able 72: (s1buf) s erial p ort 1, d ata b uffer - sfr c1 h 7 6 5 4 3 2 1 0 s1buf [7:0] as is the case with uart0, uart1 includes a double buffering feature in order to avoid overwriting of the receive r egister. uart1 control register uart1 is controlled by the s1con register . the following t able provides a description of the uart1 control register. t able 73: (s1con) s erial p ort 1, c ontrol r egister - sfr c0 h 7 6 5 4 s1m reserved mpc e1 r1en 3 2 1 0 t1b8 r1b8 t1i r1i bit mnemonic function 7 s1m operation mode select 6 reserved - 5 mpce1 1 = enables multiprocessor communication feature. 4 r1en if set, enables serial reception. cleared by software to disable reception. 3 t1b8 t he 9 th transmitted data bit in mode a. set or cleared by the cpu, depending on the function it performs (parity check, multiprocessor communication, etc.) 2 r1b8 in mode a, it is the 9 th data bit received. in mode b, if sm21 is 0, rb81 is the stop bit. mu st be cleared by software. 1 t1i transmit interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software 0 r1i receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software uart1: operating modes the vmx51c1020 uart1 has two o perating modes , a and b , which provide 9 or 8 - bit operation , respectively (see following table) . t able 74: uart1 m odes sm mode description baud rate 0 a 9 - bit uart variable 1 b 8 - bit uart variable uart1 - mode a in this mode, 11 bits are transmitted or received. these 11 bits are composed of: o a start bit (logic low) , o 8 bits of data (lsb first), o a programmable 9 th bit, o s top bit (logic high) . as in mode 2 and 3 of uart0, t h e 9 th bit is used for parity . for data transmission, the tb81 bit of the s1con register holds the 9 th bit. in the case of reception, the 9 th bit will be captured into the r1b8 bit of the s1con register. uart1 - mode b in this mode, 10 bits are transmi tted and consist of: o a start bit (logic low) o 8 bits of data ( lsb first) ; o a stop bit (logic high) . received data (8 - bit) is read via the s1buf register . r eception is completed once the stop bit sets the r1b8 flag in the s1con register. uart1 - baud r ate generator as previously mentioned , uart1 ?s clock source is derived from a dedicated 10 - bit baud rate generator module. the s1rel registers are used to adjust the baud rate of uart1. t able 75: (s1rell) uart1, r eload r egister , l o w b yte - sfr be h 7 6 5 4 3 2 1 0 s1rell [7:0] t able 76: (s1relh) uart 1, r eload r egister , h igh b yte - sfr bf h 7 6 5 4 3 2 1 0 s1relh [7:0]
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 42 of 80 the following formulas are used to calculate the baud rate , s1rell and s1relh value s. seri al 1 baud rate= f clk__________ 32 x (1024 - s1rel) note: s1rel.9 - 0 = s1relh.1 - 0 + s1rell.7 - 0 s1rel = 1024 - f clk__________ 32 x baud rate t able 77: s erial 1 b aud r ate s ample v alues desired baud rate s1rel @ f clk = 11.0592 mhz s1rel @ f clk = 14.746 mhz 500.0 kbps - - 460.8 kbps - 3ffh 230.4 kbps - 3feh 115.2 kbps 3fdh 3fch 57.6 kbps 3fah 3f8h 19.2 kbps 3eeh 3e8h 9.6 kbps 3dch 3d0h 2.4 kbps 370h 34fh 1.2 kbp s 2e0h 280h setting up and using uart1 in order to use uart1, the following operations must be performed: o enable the uart1 interface o set i/o pad direction tx= output, rx=input o enable reception (if required) o configure the uart1 controller s1con examp le of uart1 setup and use the following are c code examples of uart1 configuration , serial byte transmission and interrupt usage. // ---------------------------------------------------------------------------------------- // // uart1 config // // configure the uart1 to operate in rs232 mode at 115200bps // with a crystal of 14.7456mhz // ---------------------------------------------------------------------------------------- // void uart1config(void) { p0pincfg |= 0x04; // pads for uart 1 digpwren |= 0x02 ; // enable uart1 s1rell = 0xfc; // set com speed = 115200bps s1relh = 0x03; s1con = 0x90; // mode b, receive enable }//end of uart1config() function // ---------------------------------------------------------------------------------------- // // txm it1 -- transmit one byte on the uart1 // ---------------------------------------------------------------------------------------- // void txmit1( unsigned char charact){ s1buf = charact; userflags = s1con; while (!uart_tx_empty) {userflags = s1con;} //wait tx empty flag s1con = s1con & 0xfd; //clear both r1i & t1i bits }//end of txmit1() function // ---------------------------------------------------------------------------------------- // // interrupt configuration // ----------------------------- ---------------------------------------------------------- // ien0 |= 0x80; // enable all interrupts ien2 |= 0x01; // enable interrupt uart 1 // ---------------------------------------------------------------------------------------- // // interrupt fun ction // ---------------------------------------------------------------------------------------- // void int_serial_1 (void) interrupt 16 { ien0 &= 0x7f; // disable all interrupts /* ------------------------ */ /*interrupt code here*/ /* ------------------------ */ if (s1con&0x01==0x01) { s1con &= 0xfe; // clear ri (it comes // before t1i) } else { s1con &= 0xfd; // clear t1i } ien0 |= 0x80;} // enable all interrupts } } / ------------------------------------------------------------- ----------
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 43 of 80 uart1 driven differential transceiver the vmx51c1020 includes a differential transceiver compatible with the j1708/rs - 485/rs - 422 standards . these are driven by uart1. the transceiver?s signals are differential which provide high electrical noise immunity . the differential interface is capable of transferring/recieving data over hundreds of feet o f twisted pair wire. a number of devices can be connected in parallel to the differential bus in order to implement a multi - drop network. the nu mber of devices that can be networked depends on the bus length and configuration. the admissible common mode voltage range of the differential interface is ? 2.0 v to +7.0 v. when implementing this type of transmission network over long distance s in noi sy environment s , appropriate protection is recommended in order to prevent the common mode voltage from causing any damage to the vmx51c1020 . f igure 27: d ifferential i nterface (j1708 config ) +5v +5v versa mix tx1d+ rx1d+ tx1d- rx1d- f igure 28: d ifferential i nterfac e (rs485 config ) +5v versa mix tx1d+ rx1d+ tx1d- rx1d- from the software point of view, the differential transceiver is viewed as differential uart. the differential tr ansceiver i/os are connected to uart1 of the vmx51c1020 , therefore communication parameters su ch as the data length, speed, etc are managed by the uart1 peripheral inte rface /registers . using the uart1 differential transceiver in order to use the differential transceiver interface, one must perform the following operations: o enable uart1 and the differential interface by setting b it s 1 and 2 of the digpwren register . o configure uart1?s operating mode via the s1con register. o set the b aud r ate via the s1relh and s1rell registers. o enable uart1 ?s interrupt , if required use uart1 ?s s1buf register to transmit and receive data through the differential transceiver. if the p0.2 pin is configured as an output, the signal corresponding to the tx1 signal of uart1 will appear on this pin (note that the p0.3 - rx1 pin can be used as regular digital output ) . wh en the transceiver is connected in half - duplex mode (rx1d+ connected to tx1d+ and rx1d - connected to tx1d - ) and uart1 ?s interrupts are enabled, careful management of the uart1 interrupts will be required as every byte transmitted will generate a local rx i nterrupt.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 44 of 80 differential interface use example the following code provides and an example of configuration and use of the vmx51c1020 differential interface. #pragma small #pragma unsignedchar #include // --- function prototypes void txmi t1( unsigned char charact); void uart1differential(void); // - global variables // - constants definition sbit uart_tx_empty = userflags^1; code char irq0msg[]=" ramtron inc?; // -------------------------------------------------------------------------- ------------------- // // main function // --------------------------------------------------------------------------------------------- // at 0x0100 void main (void) { // enable and configure the uart1 uart1dif ferential(); //config uart1 diff interface // warning : the clock control circuit does affect the dedicated baud rate // generator s0rel, s1rel and timer1 operation //*** configure the interrupts ien0 |= 0x81; //enable interrupts + ext. 0 interrupt ien2 |= 0x01; //enable uart1 interrupt txmit1(?a?); //transmit one character on uart1 do { }while(1); //wait for uart1 rx interrupt }// end of main()... // ------------------------------------------------------------------ --------------------------- // // uart1 differential interface interrupt // // in this example, the source of uart1 interrupt would be caused // by bytes reception on the differential interface // ------------------------------------------------------------ ---------------------------------- // void int_uart1 (void) interrupt 16 { unsigned char charact; ien0 &= 0x7f; // -- put you code here? s1con = s1con & 0xfc; //clear both r1i & t1i bits ien0 |= 0x80; // enable all interrupts }// end of uart 1 interrupt // --------------------------------------------------------------------------------------------- // // ext int0 interrupt // // // when the external interrupt 0 is triggered a message string is sent over the // the serial uart1 // ---------- ----------------------------------------------------------------------------------- // void int_ext_0 (void) interrupt 0 { int x=0; idata unsigned char cptr=0x01; ien0 &= 0x7f; //disable ext0 interrupt cptr = cptr - 1; while( irq0msg[cptr] ! = ' \ n') //send a text string over the differential interface { txmit1( irq0msg[cptr]); cptr = cptr +1; } ien0 = 0x81; //enable all interrupts + int_0 // -------------------------------------------------------------------------------- -------------------- // // ------------------------------- individual functions ---------------------------------------- // // ---------------------------------------------------------------------------------------------------- // // --------------------------- ------------------------------------------------------------------------- // // uart1 differential config // // configure the uart1 differential interface to operate in // rs232 mode at 115200bps with a crystal of 14.7456mhz // // -------------------------- -------------------------------------------------------------------------- // void uart1differential(void) { digpwren |= 0x06; // enable uart1 & differential transceiver p0pincfg |= 0x04; // pads for uart1 p0pincfg = 0x00; s1rell = 0xfc; // set com speed = 115200bps s1relh = 0x03; s1con = 0x90; // mode b, receive enable }//end of uart1differential() function // ----------------------------------------------------------------------------------------------- // // txmit1 // // transmit one byte on t he uart1 differential interface // // ----------------------------------------------------------------------------------------------- // void txmit1( unsigned char charact){ s1buf = charact; userflags = s1con; //wait tx empty flag to be raised while (! uart_tx_empty) {userflags = s1con;} s1con = s1con & 0xfd; //clear both r1i & t1i bits }//end of txmit1() function
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 45 of 80 spi interface the v mx 51c1020 ?s spi peripheral is a highly configurable and powerful interface enabling high speed serial data exchange with external devices such as a/d s , d/a a , eeprom s, etc. the spi interface can operate as either a master or a slave device. in master mode, it can control up to 4 slave devices connected to the spi bus. the following list s a number of the vmx51c1020?s spi features . o allows synchronous serial data transfers o transaction size is configurable from 1 - 32 - bits and more. o full duplex support o spi modes 0, 1, 2, 3 and 4 supported (full clock polarity and phase control) o up to four slave devices can be connected to the spi bus when it is configured in master mode o s lave mode operation o data transmission speed is configurable o double 32 - bit buffers in transmission and reception o 3 dedicated interrupt flags o tx - empty o rx data available o rx overrun o automatic/manual control o f the chip selects lines. o spi operation is not affected by the clock control unit the following provides a block diagram view of the spi interface. f igure 29: spi i nterface b lock d iagram processor spi sfrs spi irqs versa mix spi interface serial data in serial data out serial clock in/out sdi sdo sck cs0 cs1 cs2 cs3 ss chip select output chip select output chip select output slave select input chip select output to slave device #1 to slave device #2 to slave device #3 to slave device #4 from master device spi transmit/receive buffer structur e when receiving data , the first byte received is stored in the spirx0 buffer. as bits continue to arrive , the data already present in the buffer is shifted towards the least significant byte end of the receive registers (see following figure). for exam ple (see following figure) , assume the spi is about to receive 4 consecutive bytes of data: w, x, y and z, where the first byte received is byte w , the first received byte (w) will be placed in the spirx0 register . upon reception of the next byte (x), th e contents of spirx0 will be shifted into sfr register spirx1 and byte x will be placed in the spirx0 registers. following th is same procedure, we bytes w, x, y and z will end up in rx data buffer registers spirx0, spirx1, spirx2 and spirx3 , respectively. the case where the sdo and sdi pins are shorted together is represented in the following diagram.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 46 of 80 f igure 30 : spi i nterface r eceive t ransmit s chematic w z y x rx data buffer tx data buffer close-up view of how the bits within the byte is placed after it has been received 7 6 5 4 3 2 1 0 msbit lsbit bytes are shifted 1 byte position at a time each time a new byte is received w z y x rx data buffer tx data buffer 0 1 2 3 4 5 6 7 lsbit msbit before a reception spitx3 spirx0 spitx0 spirx3 after a reception first byte to be transmitted spirx3 spitx3 spirx0 spitx0 first byte received is placed in the least significant byte register msb msb lsb lsb lsb lsb msb msb spirx2 spirx1 spitx2 spitx1 spitx2 spitx1 spirx2 spirx1 when using the spi interface, it is important to keep in mind that a t ransmission is start ed when the spirx3tx0 register is written t o. from an sfr point of view, the transmission and reception buffers of the spi interface occupy the following addresses. t able 78: (spirx3tx0) spi d ata b uffer , l ow b yte - sfr e1 h 7 6 5 4 3 2 1 0 spirx3tx0 [7:0] bit mnemonic function spitx0 spi transmit data bits 7:0 7 - 0 spirx3 spi receive data bits 31:24 t able 79: (spirx2tx1) spi d ata b uffer , b yte 1 - sfr e2 h 7 6 5 4 3 2 1 0 spirx2tx1 [15:8] bit mnemonic function spitx1 spi 1 transmit data bits 15:8 15:8 spirx2 spi receive 1 data bits 23:16 t able 80: (spirx1tx2) spi d ata b uffer , b yte 2 - sfr e3 h 7 6 5 4 3 2 1 0 spirx1tx2 [23:16] bit mnemonic function spitx2 spi transmit data bits 23:16 22:16 spirx1 spi receive data bits 15:8 t able 81: (spirx0tx3) spi d ata b uffer , h igh b yte - sfr e4 h 7 6 5 4 3 2 1 0 spirx0tx3 [31:24] bit mnemonic function spitx3 spi transmit data bits 31:24 31:24 spir x0 spi receive data bits 7:0 spi control registers the spi control registers are used to define: o spi operating speed (master mode) o a ctive chip select output (master mode) o spi clock phase (master/slave modes). o spi clock polarity (master/slave modes). t able 82: (spictrl) spi c ontrol r egister - sfr e5 h 7 6 5 4 spick [2:0] spics_1 3 2 1 0 spics_0 spickph spickpol spima_sl bit mnemonic function 7:5 spick[2:0] spi clock control 000 = osc ck div 2 001 = osc ck div 4 010 = osc ck di v 8 011 = osc ck div 16 100 = osc ck div 32 101 = osc ck div 64 110 = osc ck div 128 111 = osc ck div 256 4:3 spics[1:0] active cs line in master mode 00 = cs0 - active 01 = cs1 - active 10 = cs2 - active 11 = cs3 - active 2 spickph spi clock phase 1 spickp ol spi clock polarity 0 ? ck polarity is low 1 ? ck polarity is high 0 spima_sl master / - slave 1 = master 0 = slave
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 47 of 80 spi operating speed three bit in the spictrl register serve to adjust the communication speed of the spi interface. spick[2:0] div ratio fosc = 14.74mhz fosc = 11.059mhz clk div 2 7.37 mhz 5.53 mhz clk div 4 3.68 mhz 2.76 mhz clk div 8 1.84 mhz 1.38 mhz clk div 16 922 khz 691 khz clk div 32 461 khz 346 khz clk div 64 230 khz 173 khz clk div 128 115 khz 86 khz clk div 256 57.6 khz 43.2 khz spi master chip select control when the spi is configured in master mode, the value of the spics[1:0] bits will define which chip select pins will be active during the transaction. t he following sections will describe how the spi clock po larity and phase affect s the read and writ e operations of the spi interface. spi operating modes the spi interface can operate in four distinct modes defined by the spickph and spickpol bits of the spictrl register. spickph defines the spi clock phase and spickpol defines the clock polarity for data exchange . spickpol bit value spickph bit value spi operating mode 0 0 spi mode 0 0 1 spi mode 1 1 0 spi mode 2 1 1 spi mode 3 spi mode 0 o data is placed on the sdo pin at the rising edge of the clock. o data is sampled on the sdi pin at the falling edge of the clock. f igure 31 : spi m ode 0 msb lsb cs x sck sdi sdo spi mode 0: spickpol =0,spickph =0 *arrows indicate the edge where the data acquisition occurs spi mode 1 o data is placed on the sdo pin at the falling edge of the clock. o data is sampled on the sdi pin at the rising edge of the cl ock. f igure 32: spi m ode 1 cs x sck sdi sdo spi mode 1: spickpol =0,spickph =1 msb lsb *arrows indicate the edge where the data acquisition occurs
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 48 of 80 spi mode 2 o data is placed on the sdo pin at the falling edge of the clock. o data is sampled on the sdi pin at the rising edge of the clock. f igure 33: spi m ode 2 cs x sdi sdo spi mode 2: spickpol =1,spickph =0 sck msb lsb *arrows indicate the edge where the data acquisition occurs sp i mode 3 o data is placed on the sdo pin at the rising edge of the clock. o data is sampled on the sdi pin at the falling edge of the clock. f igure 34: spi m ode 3 cs x sdo spi mode 3: spickpol =1,spickph =1 sck sdi msb lsb *arrows indicate the edge where the data acquisition occurs spi transaction size m any spi based microcontrollers only allow a fixed spi transaction size of 8 - bits. however, most devices requiring spi control require transactions of more than 8 - bits , giving way to alternate inefficient means of dealing with spi transactions . the vmx51c1020 spi interface includes a t ransaction size control register , spisize that enables different sized transaction to be performed. t he spi interface also automatically control s the chip select line. the following table describes the spisize register. t able 83: (spisize) spi s ize c ontrol r egister - sfr e7 h 7 6 5 4 3 2 1 0 spisize[7:0] bit mnemonic function 7:0 spisize[7:0] value of the spi packet size the following formula is used to calculate the transaction size. for spisize from 0 to 31: spi transaction size = [s pisize + 1] for spisize from 32 to 255*: spi transaction size = [spisize*8 - 216] an spi transaction size greater than 32 bits is possible when using the vmx51c1020 spi interface , h owever, large data packets of this size require careful managemen t of the associated interrupt s in order to avoid buffer overwrites.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 49 of 80 spi interrupts the spi interface has three associated interrupt s. o spi rx overrun o spi rx data available o spi tx empty the spirxovie, spirxavie and spitxempie bits of the spiconfig re gister allow individual enabl ing of the above interrupt sources at the spi interface level. at the processor level, two interrupt vectors are dedicated to the spi interface: o spi rx data available and overrun interrupt o spi tx empty interrupt in order to have the processor jump to the associated interrupt routine, you must also enable one or both of these interrupts in the ien1 register as well as set the ea bit of the ien0 register (see interrupt section). t able 84: (spiconfig) spi c onfig r egister - sfr e6 h 7 6 5 4 spicslo - fsoncs3 spiload 3 2 1 0 - spirxovie spirxavie spitxempie bit mnemonic function 7 spicslo manual cs up (master mode) 0 = the csx goes low when transmission begins and returns to high when it ends. 1 = the csx stays low after transmission ends. the user must clear this bit for the csx line to return high. 6 - - 5 fsoncs3 this bit sends the frame select pulse on cs3. 4 spiload this bit sends load pulse on cs3. 3 - - 2 spirxovie spi receiver overrun inte rrupt enable. 1 spirxavie spi receiver available interrupt enable. 0 spitxempie spi transmitter empty interrupt enable. the spiirqstat register contains the interrupts flags associated with the spi interface. monitoring these bits allows polling the control of the spi interface . t able 85: (spiirqstat) spi i nterrupt s tatus r egister - sfr e9 h 7 6 5 4 - - spitxempto spislavesel 3 2 1 0 spisel spiov spirxav spitxemp bit mnemonic function 7:6 - - 5 spitxempto flag that indicate s that we have not reloaded the transmit buffer fast enough (only used for packets greater than 32 bits.). 4 spislavesel slave select ?not? (ssn) 3 spisel this bit is the result of the logical and operation between cs0, cs1, cs2 and cs3. (indicates if on e chip is selected.) 2 spiov spi receiver overrun 1 spirxav spi receiver available 0 spitxemp spi transmit buffer is ready to receive mode data. it does not flag that the transmission is completed. spi manual chip select control in some application s , manual control of the active select line can be useful. setting the spicslo bit of the spiconfig register force s the active chip select line to stay low when the spi transaction is completed in master mode. when the spicslo bit is cleared, the chip se lect line return s to its inactive state . spi manual load control the spi can generate a load pulse on the cs3 pin when the spiload bit is set. this is useful for s ome d/a converters and avoids having to use a separate i/o pin for th is purpose.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 50 of 80 spi fr ame select control it?s also possible to generate a positive pulse on the cs3 pin of the spi interface by setting the fsoncs3 bit of the spiconfig register. this feature can be used to generate a frame select signal required by some dsp compatible devices without requiring the use of a separate i/o pin. note that when both the spiload and fsoncs3 are selected, the internal logic give priority to the frame select pulse . spi interface to 16 - bit d/a example the following is a code example for doing 16 - bit transfers over the the spi interface. // --------------------------------------------- // // vmix_spi_to_dac_interface. c // // --------------------------------------------- // // // this demonstration program show the how to interface a 16 - bit d/a // to the vmx51c1020 spi interface. // #pragma small #include // --- function prototypes //function prototype: send data to the 16 bit d/a void send16bitdac( unsigned char valhigh, unsigned char vallow); // bit definition sbit spi_tx_empty = userflags^0; // ------------------------------------------------------------------------------ // // main function // // ------------------------------------------------------------------------ ----- // at 0x0100 main (void) { unsigned char dacvall=0; //lsb of current dac value unsigned char dacvalh=0; //msb of current dac value digpwren |= 0x08; //enable spi interface //*** initialise the spi interface **** p2pincfg |= 0x68; // confi g i/o port to allow the spi //interface to access the pins // in this application we only need to configure the 5 upper bit of p2pincfg // p2pincfg bit 7 - sdien = 0 - > input (not used) // p2pincfg bit 6 - sdoen = 1 - > output to dac sdi pin // p2pi ncfg bit 5 - scken = 1 - > output to dac sck pin // p2pincfg bit 4 - ssen = 0 - > input (not used) // p2pincfg bit 3 - cs0en = 1 - > output to dac cs pin // p2pincfg bit 2 - cs1en = 0 - > input (not used) // p2pincfg bit 1 - cs2en = 0 - > input (no t used) // p2pincfg bit 0 - cs3en = 0 - > input (not used) spictrl = 0x25; // spi ctrl: osc/16, cs0, phase=0, pol=0, master // spick bit 7:5 = 001 - > spi clk speed = osc/2 // spics bit 4:3 = 00 - > cs0 line is active // spic kph bit 2 = 1 spi clk phase // spickpol bit 1 = 0 spi clock polarity // spima_sl bit 0 = 1 - > set spi in master mode spiconfig = 0x00; // spi config: auto cslo, no fs, no load, clear irq flags // spicslo bit 7 = 0 automatic ch ip select control // unsused bit 6 = 0 // fsoncs3 bit 5 = 0 do not send frameselect signal on cs3 // spiload bit 4 = 0 do not sen the low pulse on cs3 // unused bit 3 = 0 // spirxovie bit 2 = 0 dont enable spi rx overrun irq // spi rxavie bit 1 = 0 dont enable spi rx availlable irq // spitxempie bit 0 = 0 dont enable spi tx empty irq spisize = 0x0f; // spi size: 16 - bits // generate a triangle wave on the dac output while(1){ do{ dacvall = dacvall + 1; if( dacvall==0xf f) { dacvalh = dacvalh +1; dacvall = 0x00; } send16 - bitdac( dacvalh, dacvall); }while( (dacvall != 0xff) && (dacvalh != 0xff) ); do{ dacvall = dacvall - 1; if( dacvall==0x00) { dacvalh = dacvalh - 1; dacvall = 0xff; } send16 - bitda c( dacvalh, dacvall); }while( (dacvall != 0x00) && (dacvalh != 0x00) ); }; }// end of main()... // ----------------------------------------------------------------------- // // send16 - bitdac - send data to 16 bit d/a converter // // ---------------- ------------------------------------------------------- // void send16 - bitdac( unsigned char valhigh, unsigned char vallow){ // userflags = 0x00; // while(!spi_tx_empty){userflags = spiirqstat;} spirx2tx1 = vallow; //put lsb of value in spi transmit bu ffer // - > trigger transmission spirx3tx0 = valhigh; //put msb of value in spi transmit buffer // - > trigger transmission do{ //wait spi tx empty flag to be activated userflags = p2; userflags &= 0x08; }while( userflags == 0); } //end of send16 - bitdac
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 51 of 80 spi interrupt example the following provides an example of basic spi configuration and interrupt handling. // ------------------------------------------------------------------------------- // // sample c code for spi rx & tx i nterrupt set - up // ------------------------------------------------------------------------------- // // #pragma small #include at 0x0100 main (void) { digpwren = 0x08; // enable spi p2pincfg = 0x4f; // set pads direction spiconfig = 0x03; // enable rx_avail + tx_empty spisize = 0x07; // spi size: 8 bits ien0 |= 0x80; // enable all interrupts ien1 |= 0x06; // enable spi txempty + rxavail interrupt spirx3tx0 = valhigh; //put msb of value in spi transmit buffer // - > trigger transm ission do{ }while(1) }//end of main() // --------------------------------------------------------------------------- // // spi tx empty interrupt function // --------------------------------------------------------------------------- // void int_2_spi _tx (void) interrupt 9 { ien0 &= 0x7f; // disable all interrupts /* ------------------------- */ /* interrupt code here*/ /* ------------------------- */ ircon &= 0xfd; // clear flag spitxif ien0 |= 0x80; // enable all interrupts } // -------------- ------------------------------------------------------------- // // spi rx availlable function // --------------------------------------------------------------------------- // void int_2_spi_rx (void) interrupt 10 { ien0 &= 0x7f; // disable all interrupt s /* ------------------------- */ /* interrupt code here*/ /* ------------------------- */ ircon &= 0xfb; // clear flag spirxif ien0 |= 0x80; // enable all interrupts } // --------------------------------------------------------------------------- // due to the double buffering of the spi interface, a n spi tx empty interrupt will be activated as soon as the data to be transmit ted is written into the spi interface transmit buffer. i f data is subsequently written into the spi transmit buffer befor e the original data has been transmitted, the tx empty interrupt will only be activated when the original data has been fully transmitted. the spi also includes double buffering for data reception . o nce a data reception is completed , the rx interrupt is acti vated and the data is transferred into the spi rx buffer. at this point, the spi interface can receive more data. however, the processor must have retrieved the first data stream before the second data stream reception is complete , o therwise a data overru n will occur and the spi rx overrun interrupt will be activated , if enabled.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 52 of 80 i2c interface the vmx51c1020 includes an i2c compatible communication interface that can be configured in master mode or in slave mode. i 2 c control registers the i2crxtx sfr re gister is used to retrieve and transmit data on the i 2 c interface. t able 86: (i2crxtx) i2c d ata b uffer - sfr de h 7 6 5 4 3 2 1 0 i2crxtx [7:0] bit mnemonic function 7:0 i2crxtx[7:0] i2c data receiver / transmitter buffer the i2cco nfig register serves to configure the operation of the vmx51c1020 i 2 c interface. the following table describes the i2cconfig register bit s. t able 87: (i2cconfig) i2c c onfiguration - sfr da h 7 6 5 4 i2cmaskid i2crxovie i2crxdavie i2ct xempie 3 2 1 0 i2cmanack i2cackmode i2cmstop i2cmaster bit mnemonic function 7 i2cmaskid this is used to mask the chip id when you have only two devices. therefore in a transaction, rather that receiving the chip id first, you will receive the first packet of data. 6 i2crxovie i2c receiver overrun interrupt enable 5 i2crxdavie i2c receiver available interrupt enable 4 i2ctxempie i2c transmitter empty interrupt enable 3 i2cmanack 1= manual acknowledge line goes to 0 0= manual acknowledge line goes to 1 2 i2cackmode used only with master rx, master tx, and slave rx. 1= manual acknowledge on 0= manual acknowledge off 1 i2cmstop i2c master receiver stops at next acknowledge phase. (read during data phase) 0 i2cmaster i2c master mode enable 1= i2c in terface is master 0= i2c interface is slave the i2cirqstat register provides the status of the i 2 c interface operation and monitors the i 2 c bus status. t able 88: (i2cirqstat) i2c i nterrupt s tatus - sfr dd h 7 6 5 4 i2cgotstop i2cnoa ck i2csda i2cdatack 3 2 1 0 i2cidle i2crxov i2crxav i2ctxemp bit mnemonic function 7 i2csgotstop this means that the slave has received a stop (this bit is read only). reset only when the master begins a new transmission. 6 i2cnoack flag that indica tes that no acknowledge has been received. is reset at the start of the next transaction 5 i2csda value of sda line. 4 i2cdatack data acknowledge phase. 3 i2cidle indicates that i2c is idle 2 i2crxov i2c receiver overrun 1 i2crxav i2c receiver availa ble 0 i2ctxemp i2c transmitter empty the i2cchipid register holds the vmx51c1020 i 2 c interface id as well as the status bit that indicates if the last byte monitored on the i 2 c interface was destined for the vmx51c1020 or not.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 53 of 80 the reset value of this r egister is 0x42, corresponding to an i 2 c chip id of 0x21. the chip id value of the vmx51c1020 can be dynamically changed by writing the desired id into the i2cchipid register (see following table) . t able 89: (i2cchipid) i2c c hip id - sfr dc h 7 6 5 4 3 2 1 0 i2cid [6:0] i2cwid bit mnemonic function 7:1 i2cid[6:0] the value of this chip?s id 0 i2wid read only and is u sed only in slave mode. 0:the . id received corresponds to the i2cid 1: the id received do not correspond to the i2c id the i2wid bit is ?read only? and used only in slave mode and is an indicator of whether the transaction is targeted to th e vmx1020 device. if the device id sent by the m aster device corresponds to the i2cid value stored in the i2cchipid, the i2wid bit will be cleared to 0 by the i2c module. i f the transaction was destined for another i2c slave device, the i2wid bit will be set to 1. the i2wid value is valid at the moment the device id transmission from the master device on the i 2 c bus has complete e . in the case where the i 2 c rx available interrupt is activated, once the device id is received, an i 2 c rx available interrupt will be triggered. the interrupt service routine should then monitor the i2wid bit in order to establish if th e transaction i s destined for this vmx1020 device. if the i2wid bit is set to 1, the i 2 c interrupt service routine can be terminated and there won?t be another i 2 c rx available interrupt until the next i 2 c transaction . i f the i2wid bit is cleared , the rx available in terrupt, if enabled, will be triggered for each data byte received. i 2 c clock speed the vmx51c1020 ?s i 2 c communication speed is fully configurable . c ontrol of the i 2 c communication speed enabled via the i2cclkctrl register. the following formula is u sed to calculate the i 2 c clock frequency in master mode . i 2 c clk = _______ _ f osc __________ [8 x (i2cclkctrl)] the following table provides examples of i 2 c clock (on scl pin) speeds for various setting of the i2cclkctrl r egister when using a 14.75mhz oscillator to drive the vmx51c1020 . i2cclkctrl value i2c clock (scl value) 01h 920khz 03h 461khz 07h 230khz 13h 92khz 27h 46khz c7h 9.2khz when the i 2 c interface is configured for s lave modethe i2cclkctrl is not used t able 90: (i2cclkctrl) i2c c lock c ontrol - sfr db h 7 6 5 4 3 2 1 0 i2cclkctrl [7:0] bit mnemonic function 7:0 i2cclkctrl i2c clock speed control
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 54 of 80 i 2 c interface interrupts the i 2 c interface has a dedicated interrupt vector located at address 0x5b. three flags (see below) share the i 2 c interrupt vector and can be used to monitor the i 2 c interface status making it possible to activate the i 2 c interrupt. i2ctxemp : is set to 1 when the transmit buffer is empty i2crxav: is set to 1 wh en data byte reception completes . i2crxov: is set to 1 if a new byte reception completes before the previous data in the reception buffer is read, resulting in a data collision. these flags can all trigger the i 2 c interrupt if their corresponding bit in t he i2cconfig register is set to one. in the case where more than one of these flags can activate an i 2 c interrupt, the interrupt service routine is left to fi gure out which condition generated the interrupt. note that the i2crxav, i2ctxemp and i2crxov fl ags can still be polled if their corresponding interrupt enable flag is cleared . therefore they can still be used to monitor status . master i 2 c operation in master mode, the vmx51c1020 i 2 c interface control s the i 2 c bus transfer s . in order to configure the i 2 c interface as a master, the i2cmaster bit of the i2cconfig register must be set to one. once the i 2 c interface is configured, sending data to a slave device connected to the bus is done by writing the data into the i2crxtx register. before sending data to a slave device, a byte containing the target device?s chip id and read/write bit must be sent to it. a ma ster mode data read is triggered by reading the i2crxav (bit 1) of the i2cirqstat register. the data is present on the i2crxtx register when the i2crxav bit is set. reading the value of the i2crxtx register resets the i2crxav bit. once started, the i 2 c byte read process will continue until the master generates a stop condition. when the i 2 c interface is configured as a master, setting t he i2cmstop bit of the i2cconfig register to a 1 will result in the i 2 c interface generat ing a stop condition after the reception of the next byte. in master mode, it?s possible to manually control the operation of the acknowledged timing when receiving d ata. to do this, you must first set the i2cmanack bit of the i2cconfig register to 1 . then, once you have received a byte, you can manually control the acknowledge level by clearing or setting the i2cmanack bit. note: the vmx51c1020 i 2 c interface is no t compatible with the i 2 c multi - master mode. slave i 2 c operation the vmx51c1020 i 2 c interface can be configured as a slave by clearing the i2cmaster bit of the i2cconfig register. in slave mode, the vmx51c1020 has no control over the rate or timing of th e data exchange that occurs on the i 2 c bus. therefore, in slave mode, it is preferable to manage the transactions using the i 2 c interrupts. the i2cmaskid bit, when set , will configure the slave device to mask the received id byte and receive the data dir ectly. this is useful when only two devices are present on the i 2 c bus. note: when the vmx51c1020 starts transmitting data in slave mode, it will continually transmit the value present in the i 2 c transmit register as long as the master provides the clock signal or until the master device generates a stop condition
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 55 of 80 errata: the vmx1020 i 2 c interface has a critical timing issue when the device is configured as a slave a nd transmit s multiple data bytes. single byte transmission in slave mode is not effe cted. the condition arises if the master device release s the sda line at the same time it bring s the scl line low for the acknowledge phase. in order for the vmx1020 i 2 c slave transmission to work properly for multiple bytes, the master device must relea se the sda line after the scl negative edge. for this reason i t is not possible to have a vmx1020 device configured as an i 2 c master and vmx1020 devices configured as i 2 c slaves on the same i 2 c bus. unless data transmitted from vmx1020 i 2 c slaves to the i 2 c master is done one by te at a time. i 2 c eeprom interface example program the following provides an example program us ing the vmx51c1020 i 2 c interface for perform ing r ead and w rite operations to an externally connected eeprom device. #pragma small #i nclude // --- function prototypes unsigned char eeread(idata unsigned char, idata unsigned char); void eewrite(idata unsigned char, idata unsigned char, unsigned char); // - global variables idata unsigned char irqcptr=0x00; sbit i2c_tx_em pty = userflags^0; sbit i2c_rx_avail = userflags^1; sbit i2c_is_idle = userflags^3; sbit i2c_no_ack = userflags^6; // ------------------------------------------------------------------------------- // // main function // // ------------------------------------------------------------------------------ // void main (void){ unsigned char x=0; digpwren = 0x13; //enable the i2c peripheral //*** configure i2c speed. i2cclkctrl = 0x013; // ?to about 100khz... //*** configure the interrupts ien0 |= 0x81; //enable ext int0 interrupt + main //*** infinite loop waiting for ext irq while(1){ }; }// end of main()... // ------------------------------------------------------------- ------------------ // // ext int0 interrupt // // when the external interrupt 0 is triggered read and write // operations are performed on the eeprom // ------------------------------------------------------------------------------- // void int_ext_0 (void) interrupt 0 { // local variables declaration idata unsigned char eedata; idata unsigned char adrsh =0; idata unsigned char adrsl =0; idata int adrs =0; // ien0 &= 0x7f; //disable ext0 interrupt //(masked for debugger compatibility) //write ir qcptr into the eeprom at adrs 0x0100 eewrite( 0x01,0x00,irqcptr); irqcptr = irqcptr + 1; //increment the interrupt counter //perform an eeprom read at address 0x100 eedata = eeread(0x01, 0x00); delay1ms(100); //debo delay for the switch o n int0 // ien0 = 0x81; // enable all interrupts + int_0 (removed //for debugger compatibility) }// end of ext int 0 // --------------------------------------------------------------------------------- // // individuals functions // // -------------------------------------------------------------------------------- // // ----------------------------------------------------------------- // // eeread - eeprom random read // // -------------------------------- -------------------------------- // unsigned char eeread(idata unsigned char adrsh, idata unsigned char adrsl) { idata unsigned char x=0; idata unsigned char readvalue=0;
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 56 of 80 i2cconfig = 0x03; //i2c master mode no interrupt i2crxtx = 0xa8; //send 24lc64 adrs + write command userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} i2crxtx = adrsh; //send 24lc64 adrsh userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} i2crxtx = adrsl; //send 24lc 64 adrsl userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} userflags = 0x00; //wait for i2c interface to be idle while(!i2c_is_idle){userflags = i2cirqstat;} i2cconfig &= 0xfd; //set master rx stop, only 1 byte to receive i2cc onfig |= 0x02; i2crxtx = 0xa9; // chip id read userflags = 0x00; while(!i2c_rx_avail){userflags = i2cirqstat;} readvalue = i2crxtx; userflags = 0x00; while(!i2c_is_idle){userflags = i2cirqstat;} //wait for i2c idle return readvalue; }// end of eeread // ---------------------------------------------------------------- // // eewrite - eeprom random write // // ---------------------------------------------------------------- // void eewrite(idata unsigned char adrsh, idata unsigned char adrsl, unsigned char eedata) { idata unsigned char x; i2cconfig = 0x01; //i2c master mode no interrupt i2crxtx = 0xa8; //send eeprom adrs + read //command userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} i2crxtx = adrsh; //send adrsh userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} i2crxtx = adrsl; //send adrsl userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} i2crxtx = eedata; //send 24lc64 data and wait //for i2c bus idle userflags = 0x00; while(!i2c_is_idle){userflags = i2cirqstat;} /// -- wait write operation to end i2cconfig = 0x01; //i2c master mode no interrupt do{ i2crxtx = 0xa8; //send 24lc64 adrs +read command userflags = 0x00; while(!i2c_tx_empty){userflags = i2cirqstat;} userflags = i2cirqstat; }while(i2c_no_ack); delay1ms(5); //5ms delay for eeprom write }// end of eeprom write
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 57 of 80 analog signal path the vmx51c1020 implement s a complete single chip acquisition system by integrating the following analog peripherals: o 1 2 - bit a/d converter having 4 external inputs as well as 3 internal connections to the operational amplifier and current source input and output for a total of 7 inputs . the adc conversion rate is programmable up to 10khz o internal bandgap reference and pga o 1 programmable current source o 2 digital potentiometers o 1 digital switch the following figure provides a block diagram of the vmx51c1020 ?s analog peripherals and their connection . f igure 35: a nalog s ignal p ath of the vmx51c1020 200mv 800mv ain0 ain1 ain2 ain3 pga xtvref reserved isrcin opout isrcin isrcout/ta a/d pot1 pot2 bandgap reserved unused unused sw1 opout isrcout ain0 ain1 ain2 ain3 vbgap total of 7 a/d inputs the on - chip calibrated bandgap or the external reference provides the basis for all derived on - chip voltages. these signals serve as reference for the adc and the current source. analog peripheral power control selection of the internal / external reference, the multi plexer?s current source drive, adc control, and the respective power downs for these peripherals are controlled via the analogpwren sfr registers. internal reference and pga the vmx51c1020 provides a temperature calibrated internal ban dgap reference coupled with a programmable gain amplifier. the programmable gain amplifier?s role is to amplify the bandgap output to 2.7 volts and provide the drive required for the adc reference input and current source. both the bandgap and the pga a re calibrated during production and their associated calibration registers are automatically loaded with the appropriate calibration vectors when the device is reset. the bandgap and pga calibration vectors are stored into the bgapcal and pgacal sfr reg isters when a reset occurs. it is possible for the user program to overwrite the content s of those registers. t able 91: (bgapcal) b and - gap c alibration v ector r egister - sfr b3 h 7 6 5 4 3 2 1 0 bgapcal [7:0] bit mnemonic functio n 7:0 bgapcal band - gap data calibration t able 92: (pgacal) pga c alibration v ector r egister - sfr b4 h 7 6 5 4 3 2 1 0 pgacal [7:0] bit mnemonic function 7:0 pgacal 8 msbs of pga calibration vector (lsbit is on isrccal1) using the vmx51c1020 internal reference the configuration and setup up of the vmx51c1020 ?s internal reference is done by setting bits 0 and 1 of the analogpwren register to 1. this power s on the bandgap and the pga , respectively.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 58 of 80 u se of the internal referenc e requires the addition of two external tank capacitors on the xtvref pin. th ese capacitors consist of one 4.7uf to 10uf tantalum capacitor in parallel with one 0.1uf ceramic capacitor. the following shows the connection of the tank capacitors to the xt vref pin f igure 36: t ank capacitors conne ction to the xtvref pin xtvref 4.7uf to 10uf 0.1uf 2.7v the vmx51c1020 internal reference can also be used as a n external reference provided that the load on the xtvref pin is kept to a minimum. the following table s hows the typical effect of loading on the xtvref voltage. f igure 37: t ank capacitors conne ction to the xtvref pin xtvref reference voltage (volts) load current on xtvref (ma) 2.65 2.70 2.75 0.0 1.0 2.0 3.0 4.0 5.0 it is recommended that the external load on the xtvref pin be less than 1ma. note: a stabilization delay of more than 1ms should be pro vided between the activation of the bandgap, the pga and the first a/d conversion or measurement made on the programmable current source. using an external reference an external reference can be used to drive the vmx51c1020 adc and the programmable curre nt source instead of the internal reference. the external reference voltage source can be set from 0.5 to 3.5 volts and must provide sufficient drive to operate the adc load . f igure 38: e xternal reference co nnection to the xtvref pin xtvref 4.7uf to 10uf 0.1uf v warning: when an external reference source is applied to the xtvref pin, it is mandatory not to power - on the pga. the internal bandgap reference should also be kept de - activated. reference impact on the programmable current source the progr ammable current source uses the same reference as the adc for its operation , t herefore, using an external reference will have a direct impact on the current source output. t he 200 /800 mv current source reference voltage, calibrated at 2.7v will change in a linear fashion according to the voltage present on the xtvref pin. for example, in the case where the reference voltage applied to the xtvref pin is 3v, the current source reference voltage will be scaled up by a factor of [vxtvref/2.7v] to 222mv and 88 9mv respectively. a/d converter the vmx51c1020 includes a feature rich , highly configurable on - chip 12 - bit a/d converter. the a/d conversion data is output as unsigned 12 - bit binary , with 1 lsb = full scale/4096. the following figure describes the idea l transfer function for the adc.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 59 of 80 f igure 39: i deal a/d c onverter t ransfer f unction 1111_1111_1111 0000_0000_0000 0000_0000_0001 1111_1111_1110 0000_0000_0010 0000_0000_0011 1111_1111_1101 1111_1111_1100 0v xtvref 1 lsb = xtvref / 4096 output code the a/d converter includes a system that provides the ability to trigger automatic periodic conversions of up to 10khz without processor interven tion . once the conversion is complete, the a/d system can activate an interrupt that can wake - up the processor ( assuming it has been put in to idle mode) or automatically throttle the processor clock to full speed. the vmx51c1020 a/d converter can also be configured to perform the conversion on one specific channel or on four consecutive channels (in round - robin fashion). these features make the a/d adaptable for many applications. the following paragraphs describe the vmx51c1020 ?s a/d converter regi ster features . adc data registers the adc data registers hold the adc conversion results. the adcdxlo register (s) hold the 8 least significant bits (lsb s ) of the conversion results while the adcdxhi register ( s ) hold the 4 most significant bits (msb) of t he conversion results. t able 93: (adcd0lo) adc c hannel 0 d ata r egister , l ow b yte - sfr a6 h bit mnemonic function 7:0 adcd0lo adc channel 0 low t able 94: (adcd0hi) adc c hannel 0 d ata r egister , h igh b yte - sfr a 7 h bit mnemonic function 3:0 adcd0hi adc channel 0 high t able 95: (adcd1lo) adc c hannel 1 d ata r egister , l ow b yte - sfr a9 h 7 6 5 4 3 2 1 0 adcd1lo [7:0] bit mnemonic function 7:0 adcd1lo adc channel 1 low t able 96: (adcd1hi) adc c hannel 1 d ata r egister , h igh b yte - sfr aa h 7 6 5 4 3 2 1 0 - - - - adcd1hi [3:0] bit mnemonic function 3:0 adcd1hi adc channel 1 high t able 97: (adcd2lo) adc c hannel 2 d ata r egister , l ow b yte - sfr ab h 7 6 5 4 3 2 1 0 adcd2lo [7:0] bit mnemonic function 7:0 adcd2lo adc channel 2 low t able 98: (adcd2hi) adc c hannel 2 d ata r egister , h igh b yte - sfr ac h 7 6 5 4 3 2 1 0 - - - - adcd2hi [3:0] bit mnemonic function 7:4 - - 3:0 adcd2 hi adc channel 2 high t able 99: (adcd3lo) adc c hannel 3 d ata r egister , l ow b yte - sfr ad h 7 6 5 4 3 2 1 0 adcd3lo [7:0] bit mnemonic function 7:0 adcd3lo adc channel 3 low t able 100: (adcd3hi) adc c hannel 3 d a ta r egister , h igh b yte - sfr ae h 7 6 5 4 3 2 1 0 - - - - adcd3hi [3:0] bit mnemonic function 7:4 - - 3:0 adcd3hi adc channel 3 high adc input selection a/d conversions can be performed on a single channel , sequentially on the four lower channels , o r sequentially on the four upper channels of the adc input multiplexer. an input buffer is present on each of the four external adc inputs (adin0 to ain3) these buffers must be enabled before a conversion can take place on the adc ain0 -
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 60 of 80 ain3 inputs. the se buffers are e nabling by setting the corresponding bits of the lower nibble (aien [3:0]) of the inmuxctrl register to 1 . t able 101: (inmuxctrl) a nalog i nput m ultiplexer c ontrol r egister - sfr b5 h 7 6 5 4 3 2 1 0 - adcinsel [2:0] aine n [3:0] bit mnemonic function 7 - - 6:4 adcinsel[2:0] adc input select 000 - ain0 001 - ain1 010 - ain2 011 - ain3 100 - opout 101 - vsr 110 - isrcin 111 - isrcout 3:0 ainen[3:0] analog input enable the upper four bits of the inmuxctrl register are used to define the channel on which the conversion will take place when the adc is set to perform the conversion on one specific channel. adc control register the adcctrl register is the main register used for control and operation of the adc . t able 102: (adcctrl) adc c ontrol r egister - sfr a2 h 7 6 5 4 adcirqclr xvrefcap 1 adcirq 3 2 1 0 adcie onechan cont oneshot bit mnemonic function 7 adcirqclr adc interrupt clear writing 1 clears interrupt 6 xvrefcap always keep this bit at 1 5 reserved = 1 keep this bit = 1 4 adcirq read adc interrupt flag write 1 generate adc irq 3 adcie adc interrupt enable 2 onechan 1 = conversion is performed on one channel specified adcinsel 0 = conversion is performed on 4 adc channels 1 cont 1 = enable adc continuous conversion 0 oneshot 1 = force a single conversion on 1 or 4 channels adc continuous/one shot conversion the cont bit sets the adc conversion mode. when the cont bit is set to 1, the adc will implement continuous conversion s at a rate defined by the conversion rate register. when the cont bit is set to 0, the a/d operates in ?one shot? mode , initiating a conversion when the oneshot bit of the adccontrl register is set. adc one channel/ four channel conversion the vmx51c1020 ?s adc includes a feature that renders it possible to perform a conversion on one specific channel or on four consecutive channels. this feature minimizes the load on the processor when reading more than one adc input is required. the onechan bit of the ad cctrl register controls this feature. when the onechan is set to 1, the conversion will take place on the channel selected by the inmuxctrl register. once the conversion is completed, the result will be put into the adcd0lo and adcd0hi registers when the onechan bit is set to 0, the conversion, once triggered, will be done sequentially on four channels and the conversion results will be placed into the adcdxlo and adcdxhi registers. b it 6 of the inmuxctrl register controls whether the conversion will tak e place on the four upper channels of the input multiplexer or the 4 lower channels .
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 61 of 80 adc clock source configuration a/d converter derives its clock source from the main vmx51c1020 clock. the frequency of the adc clock should be set between 250khz to 1. 25mhz c onfiguration of the adc clock source frequency is done by adjusting the value of the adcclkdiv register. the following equation is used to calculate the adc reference clock value. adc clock reference equation: adc clk ref = f osc 4x (adccdiv +1) the adc conversion requires 111 adc clock cycles to perform the conversion on one channel. the following table provides recommended adcclkdiv register value s versus conversion ra te. the numbers given are conservative figures and derived from a 14.74mhz clock adcclkdiv maximum conv. rate* 0x02 10500 hz 0x03 8000 hz 0x05 5000 hz 0x07 4000 hz 0x08 3500 hz 0x09 3200 hz 0x0b 2500 hz 0x0d, 0x0e, 0x0f 2200 hz * the maximum co nversion rate is for the single channel condition . if the conversion is performed on 4 channels, divide the maximum conversion rate by 4. for example to perform the conversion at 2 . 5 k hz on four channels, the adcclkdiv register should be set to 0x02 ( 4x 2 500hz = 10khz ) t able 103: (adcclkdiv) adc c lock d ivision c ontrol r egister - sfr 95 h 7 6 5 4 3 2 1 0 adcclkdiv [7:0] bit mnemonic function 7:0 adcclkdiv[7:0] adc clock divider adc conversion rate configuration the vmx51c1020 ?s ad c conversion rate , when configured in continuous mode is defined by the 24 - bit a/d conversion rate register that serves as the time base for trigger ing the adc conversion process. the following equation is used to calculate the value of the conversion rat e. conversion rate equation: conversion rate registers value (24 - bit) = f osc conv_rate the conversion rate register is accessible using three sfr registers as follows : t able 104: (adcconvrlow) adc c onver sion r ate r egister l ow b yte - sfr a3 h bit mnemonic function 7:0 adcconvrlow conversion rate low byte t able 105: (adcconvrmed) adc c onversion r ate r egister m ed b yte - sfr a4 h bit mnemonic function 7:0 adcconvrmed conversion rate mediu m byte t able 106: (adcconvrhigh) adc c onversion r ate r egister h igh b yte - sfr a5 h bit mnemonic function 7:0 adcconvrhigh conversion rate high byte the following table provides examples of typical value s versus conversion rate . adc conv. rate register value. con version rate fosc= 14.74mhz 1hz e10000h 10hz 168000h 100hz 024000h 1khz 003999h 2.5khz 00170ah 5khz 000b85h 8khz 000733h 10khz 0005c2h
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 62 of 80 adc status register the adc shares interrupt vector 0x6b with the interrupt on port 1 change and the compare and capture unit 3. to enable the adc interrupt, the adcie bit of the adcctrl register must be set. before or at the same time this bit is set, the adcirqclr and the adcirq bits must be cleared. t he adcpcie bit of the i en1 register must also be set , as well as the ea bit of the ien0 register. once the adc interrupt occurs, adc interrupt must be cleared by writing a ?1? into the adcintclr bit of the adcctrl register . the adcif flag in the ircon register must also be cle ared. a/d converter example the following provides example code for the a/d converter. the first section of the code covers interrupt setup / module configuration whereas the second section is the interrupt function itself . sample c code to setup the a/d converter: // ----------------------------------------------------------------------- // // main function // ----------------------------------------------------------------------- // (?) at 0x0100 void main (void) { //*** initialize the analog peripherals *** analogpwren = 0x07; //enable the following analog //peripherals: isrc, adc, pga, // bgap. ta = off (mandatory) //configure the adc and start it adcclkdiv=0x0f; //set adc clock source adcconvrlow =0x00; //configure conversion rate adcconvrmed=0x40; //= 100hz @ 14.74 mhz adcconvrhigh =0x02; inmuxctrl=0x0f; //enable all adc external inputs //buffers and select adci0 adcctrl=0xea; //configure the adc as follow: //bit 7: =1 adcirq clear //bit 6: =1 xvrefcap (always) //bit 5: =1 (always) //bit 4: =0 = adcirq (don?t care) //bit 3: =1 = adc irq enable //bit 2: =0 conversion on 4 //channels //bit 1: =1 continuous conversion //bit 0: =0 no single shot mode //*** configure the interrupts ien0 |= 0x80; //enable main interrupt ien1 |= 0x020; //enable adc interrupt while(1); //infinite loop waiting adc interrupts }// end of main()... // ----------------------------------------------------------------------- // // adc interrupt routine // ----------------------------------------------------------------------- // void int_adc (void) interrupt 13 { idata int value = 0; ien0 &= 0x7f; //disable ext0 interrupts adcctrl |=0x80; //clear adc interr upt // read adc channel 0 value = adcd0hi; value = valeur*256; value = valeur + adcd0lo; (?) // read adc channel 3 value = adcd3hi; value = valeur*256; value = valeur + adcd3lo; (?) ircon &= 0xdf; //clear adc irq flag adcctrl |=0xfa; //prepare adc for n ext acquisition ien0 |= 0x80; // enable all interrupts }// end of adc irq (?) warning: when using the adc, make sure the output multiplexer controlled by the taen bit of the analogpwren register (92h) is powered down at all times , ot herwise, the signal present on the isrcout can be routed back to the selected adc input, causing conversion error s .
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 63 of 80 programmable current source the vmx51c1020 includes a programmable current source used to drive external devices such as resistive sensors connected bet ween the isrcout and isrcin pins to ensure current output stability, the current source provides a feedback input, isrcin. the feedback is voltage controlled and can be dynamically set to either 200mv or 800mv. placing a resistor between the isrc pin and the ground defines the output current of the current source. the vmx51c1020 current source can drive current s up to 500a when the reference is set to 800mv. f igure 40: p rogrammable current source to excite sen sor 200 mv 800 mv isrcout isrcin sensor rref to a/d as shown above, a resistive device ( sensor ) must be connected between the isrcout and the isrcin. in order to perform a /d conversion of the voltage present at the terminal of the current source, there is an internal link between each of the isrcout and isrcin pins as well as the input multiplexer of the a/d converter. t able 107: (isrccal1) c urrent sour ce c alibration v ector for 200 m v feedback value - sfr bc h 7 6 5 4 3 2 1 0 pgacal0 isrccal1 [6:0] bit mnemonic function 7 pgacal0 bit 0 of pgacal 6:0 isrccal1[6:0] calibration value for isrc feedback of 200mv t able 108: (isrccal2) c urrent source c alibration v ector for 800 m v feedback value - sfr bd h 7 6 5 4 3 2 1 0 - isrccal2 [6:0] bit mnemonic function 7 - - 6:0 isrccal2[6:0] calibration value for isrc feedback of 800mv current source setup example the following provides set up examples for the current source. enabling the current source using the 200mv reference: mov analogpwren,#00110011b ;enable analog peripherals ;bit 7: opampen = 0 op - amp off ;bit 6: digpoten= 0 dig pot off ;bit 5: isrcsel = 1 isrc 800mv ;b it 4: isrcen = 1 isrc on ;bit 3: taen = 0 ta output off ;bit 2: adcen = 0 adc off ;bit 1: pgaen = 1 pga on ;bit 0: bgapen = 1 bandgap on enabling the current source using the 200mv reference: ;mov analogpwren,#00010011b ;enable an alog peripherals ;bit 7: opampen = 0 op - amp off ;bit 6: digpoten= 0 dig pot off ;bit 5: isrcsel = 0 isrc 200mv ;bit 4: isrcen = 1 isrc on ;bit 3: taen = 0 ta output off ;bit 2: adcen = 0 adc off ;bit 1: pgaen = 1 pga on ;bit 0: bgapen = 1 bandgap on
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 64 of 80 digital potentiometers the vmx51c1020 has two digital potentiometers that are control led by digpot x register s (digpot1, digpot2) that can be used in applications such as: o gain control o offset adjustment o a/d input attenuation o digit ally controlled filter f igure 41: d igital p otentiometer f unctional diagram potx b potx a digpotx register t able 109: (digpot1) d ig . p otentiometer 1 c ontrol r egister - sfr ba h 7 6 5 4 3 2 1 0 digpot1 [7:0] bit mnemonic function 7 - 0 di gpot1 potentiometer 1 value t able 110: (digpot2) d ig . p otentiometer 2 c ontrol r egister - sfr bb h 7 6 5 4 3 2 1 0 digpot2 [7:0] bit mnemonic function 7 - 0 digpot2 potentiometer 2 value the digital potentiometers are floating devic es, meaning that there are no restrictions on the voltage present on their terminals as long as they are kept within the nominal operating range of the vmx51c1020 . the current flow through the potentiometers should be limited to 5ma max. the digital pote ntiometer maximum nominal resistance is 30k +/ - 2kohms from device to device. on a given device the two digital potentiometer values usually match within 1%. before using the digital potentiometers, they must first be enabled by setting bit 6 of the ana logpwren register (92h) to 1 . t he potentiometer value is governed by the following equation. r potentiometer * = [ 256 - digpotx[7:0] ] x 30k 256 * potentiometer value digital potentiometer setup example only two instructions are required to enable and configure the digital potentiometers of the vmx51c1020 : mov analogpwren,#01000000b mov digpot1,#0c0h ;set pot1 to 25% of max pot value mov digpot2,#040h ;set pot2 to 75% of max pot value operational amp lifier the vmx51c1020 is equipped with an operational amplifier. this op - amp can be used for a wide array of analog applications such as: o gain control o offset control o reference buffering o integrator o other standard op amp applications the op - amp on the vmx5 1c1020 has an open - loop gain of 100 db ; a unity gain bandwidth of 5mhz and it is able to drive a 1ko and 40pf load. the slew rate of the op - amp is 7v/s and t he output voltage can swing between 25mv and 4.975 volts ( 10k o load ) . to activate the operational amplifier , the opampen bit (bit 7) of the analogpwren register (sfr 92h) must be set to 1. warning: if the vmx51c1020 op - amp inputs are left floating, it should be kept in power down to prevent risk of oscillation.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 65 of 80 digitally controlled switches t he vmx51c1020 include a digital switch composed of 4 sub - switches connected in parallel. these sub - switches can be individually controlled by writing to the sfr register at b7h. f igure 42: switch f unctional diagram sw1b sw1a sw1d sw1c sw1b sw1a x x x x switchctrl register the switch ?on? resistance is between 50 and 100 ohms depending on the number of sub - switches being used. if, for example, one sub - switch is closed, the switch resistance will be about 100 ohms, and if all 4 switches are closed, the switch resistance will go down to about 50 ohms. t able 111: (switchctrl) u ser s witches c ontrol r egisters - sfr b7 h 7 6 5 4 3 2 1 0 not used but implemented swtch1 [3:0] bit mnemonic function 7:4 user flags not used but implemented bits can be used as general purpo se storage 3:0 switch1[3:0] switch 1 control (composed of 4 individual switches each bit controlled) the upper 4 bits of the switchctrl register can be used as general purpose flags . analog output multiplexer the vmx51c1020?s analog output multiplexer is used for production test purposes and provid es access to internal test points of the analog signal path. . it can however, be used in applications, but due to its high intrinsic impedance, care must be taken with respect to loading. the analog output multiplexer shares its output with the current source output and therefore must be disabled when the current source or the adc is used. inversely, when the analog output multiplexer is used, the current source must be powered down. the following table s u mmarizes the analog output multiplexer select line settings. t able 112: (outmuxctrl) a nalog o utput m ultiplexer c ontrol r egister - sfr b6 h 7 6 5 4 3 2 1 0 - - - - - taoutsel [2:0] bit mnemonic function 7:3 unused unused 2:0 taoutse l[2:0] signal output on ta 000 ? ain0 001 ? ain1 010 ? ain2 011 ? ain3 100 ? vbgap 101 ? reserved 110 ? unused 111 ? unused
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 66 of 80 vmx51c1020 interrupts the vmx51c1020 is a highly integrated device incorporating a vast number of peripherals for which a com prehensive set of 29 interrupt sources sharing 12 interrupt vectors is available . most of the vmx51c1020 peripherals can generate a n interrupt, provid ing feedback to the mcu core that an event has occurred or a task has been completed. the following feat ures are key vmx51c1020 interrupt features. o each digital peripheral on the vmx51c1020 has an interrupt channel. o the spi, uarts and i2c all have event specific flag bits. o when the processor is in idle mode, an interrupt may be used to wake it up. o the p rocessor can run at full speed during interrupt routines. the following table summarizes the interrupt sources, natural priority and the associated interrupt vector addresses of the vmx51c1020 . t able 113: i nterrupt sources and natural priority interrupt interrupt vector reserved 0e43h int0 0003h uart1 0083h timer 0 000bh spi tx 004bh int1 0013h spi rx & spi rx overrun / compint0 0053h timer 1 001bh i2c (tx, rx, rx overrun) / compint1 005bh uart0 0023h mult/accu 32bit overfl ow / compint2 0063h timer 2: t2 overflow, t2ex 002bh adc and interrupt on port 1 change (8 int.) / compint3 006bh it is also possible to program the interrupts to wake - up the processor from an idle condition or force i ts clock to throttle up to full sp eed when an interrupt condition occurs. interrupt enable registers the following tables describe the interrupt enable register s their associated bit functions: t able 114: (ien0) i nterrupt e nable r egister 0 - sfr a8 h 7 6 5 4 ea wdt t 2ie s0ie 3 2 1 0 t1ie int1ie t0ie int0ie bit mnemonic function 7 ea general interrupt control 0 = disable all enabled interrupts 1 = authorize all enabled interrupts 6 wdt watchdog timer refresh flag. this bit is used to initiate a refresh of the w atchdog timer. in order to prevent an unintentional reset, the watchdog timer the user must set this bit directly before swdt. 5 t2ie timer 2 overflow / external reload interrupt 0 = disable 1 = enable 4 s0ie uart0 interrupt. 0 = disable 1 = enable 3 t1ie timer 1 overflow interrupt 0 = disable 1 = enable 2 int1ie external interrupt 1 0 = disable 1 = enable 1 t0ie timer 0 overflow interrupt 0 = disable 1 = enable 0 int0ie external interrupt 0 0 = disable 1 = enable
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 67 of 80 t able 115: (ien1) i nterrupt e nable 1 r egister - sfr e8 h 7 6 5 4 t2exie swdt adcpcie macovie 3 2 1 0 i2cie spirxovie spiteie reserved bit mnemonic function 7 t2exie t2ex interrupt enable 0 = disable 1 = enable 6 swdt watchdog timer start/refresh flag. set t o activate/refresh the watchdog timer. when directly set after setting wdt, a watchdog timer refresh is performed. bit swdt is reset. 5 adcpcie adc and port change interrupt 0 = disable 1 = enable 4 macovie mult/accu overflow 32 bits interrupt 0 = disab le 1 = enable 3 i2cie i2c interrupt 0 = disable 1 = enable 2 spirxovie spi rx avail + overrun 0 = disable 1 = enable 1 spiteie spi tx empty interrupt 0 = disable 1 = enable 0 reserved t able 116: (ien2) i nterrupt e nable 2 r egister - sfr 9a h 7 6 5 4 3 2 1 0 - - - - - - - s1ie bit mnemonic function 7 - 1 - - 0 s1ie uart 1 interrupt 0 = disable uart 1 interrupt 1 = enable uart 1 interrupt timer2 compare mode impact on interrupts the spi rx (and rxov), i 2 c, mult/accu and adc interrupts are shared with the four timer2 compare and capture unit interrupts. when the compare and capture units of timer2 are configured in compare mode via ccen register, the compare and capture unit take s control of one interrupt vector as sh own below. f igure 43: c ompare c apture i nterrupt s trucutre compint0 interrupt 0 1 interrupt vector 0053h spi rx & rxov int ccen(1,0) = 1,0 compint1 interrupt 0 1 interrupt vector 005bh i2c int ccen(3,2) = 1,0 compint2 interrupt 0 1 interrupt vector 0063h mac overflow int ccen(5,4) = 1,0 compint3 interrupt 0 1 interrupt vector 006bh adc & port change int ccen(7,6) = 1,0 the impact of this is that the corresponding peripheral interrupt, if enabled, will be blocked. the output signal from the comparison module will be routed to the interrupt system and the control lines will be dedicated to the compare and capture unit. this interrupt control ?take over? is specific to each individual compare and capture unit. for example if compare and capture unit number 2 is configured to gener ate a pwm signal on p1.2, the mult/accu overflow interrupt, if enabled, will be dedicated to the compare and capture unit number 2 and the spi, i 2 c and adc interrupts won?t be affected.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 68 of 80 interrupt status flags the ircon register is used to identify the source of an interrupt. before exiting the interrupt service routine, the ircon register bit that correspond s with the serviced interrupt should be cleared. t able 117: (ircon) i nterrupt r equest c ontrol r egister - sfr 91 h 7 6 5 4 t2 exif t2if adcif macif 3 2 1 0 i2cif spirxif spitxif reserved bit mnemonic function 7 t2exif timer 2 external reload flag this bit informs the user whether an interrupt has been generated from t2ex, if the t2exie is enabled. 6 t2if timer 2 interrup t flag 5 adcif / compint3 a/d converter interrupt request flag/ port 0 change. / compint3 4 macif / compint2 mult/accu unit interrupt request flag / compint2 3 i2cif / compint1 i 2 c interrupt request flag / compint1 2 spirxif / compint0 rx available flag spi + rx overrun / / compint0 1 spitxif tx empty flag spi 0 reserved reserved interrupt priority register all of the vmx51c1020?s interrupt sources are combined in to groups with four levels of priority . these groups can be programmed individua lly to one of the four priority levels: from level0 to level3 with level3 being the highest priority. the ip0 and ip1 register s serve to define the specific priority of each of the interrupt groups. by default, when the ip0 and ip1 registers are at reset state 00h, the natural priority order of the interrupts shown previously are i n force. t able 118: (ip0) i nterrupt p riority r egister 0 - sfr b8 h 7 6 5 4 3 2 1 0 uf8 wdtstat ip0 [5:0] bit mnemonic function 7 uf8 user flag bit 6 wd tstat watchdog timer status flag. set to 1 by hardware when the watchdog timer overflows. must be cleared manually 5 ip0.5 timer 2 port1 change adc 4 ip0.4 uart0 - mult/accu 3 ip0.3 timer 1 - i2c 2 ip0.2 external int1 - spi rx available 1 ip0.1 t imer 0 interrupt - spi tx empty 0 ip0.0 external int0 uart1 external int 0 table 119: (ip1) interrupt priority register 1 - sfr b9h 7 6 5 4 3 2 1 0 - - ip1 [5:0] bit mnemonic function 7 - - 6 - - 5 ip1.5 timer 2 port1 change adc 4 ip1.4 uart0 - mult/accu 3 ip1.3 timer 1 - i2c 2 ip1.2 external int1 - spi rx available 1 ip1.1 timer 0 interrupt - spi tx empty 0 ip1.0 external int0 uart1 external int 0 configuring the ip0 and ip1 registers makes it possible to change the priority order of the peripheral interrupts in order give higher priority to a given interrupt that belongs to a given group. t able 120: i nterrupt g roups bit interrupt group ip1.5, ip0.5 timer 2 port1 change adc ip1.4, ip0.4 uar t0 - mult/accu ip1.3, ip0.3 timer 1 - i2c ip1.2, ip0.2 external int1 - spi rx available ip1.1, ip0.1 timer 0 interrupt - spi tx empty ip1.0, ip0.0 external int0 uart1 external int 0
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 69 of 80 the respective value s of the ip1.x and ip0.x bit s define the priority level of the interrupt group vs. the other interrupt groups as follows. t able 121: i nterrupt p riority l evel ip1.x ip0.x priority level 0 0 level 0 (low) 0 1 level 1 1 0 level 2 1 1 level 3 (high) the wdtstat bit of the ip0 register is the watchdog status flag and is set to 1 by the hardware whenever a watchdog timer overflow occurs. this bit must be cleared manually. finally, bit 7 of the ip0 register can be used as a general purpose user flag.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 70 of 80 setting up int0 and i nt1 interrupts the it0 and it1 bit s of the tcon register define whether external interrupts 0 and 1 will be edge or level triggered. when an interrupt condition occurs on int0 or int1, the associated interrupt flag ie0 or ie1 will be set . the interrupt flag is automatically cleared when the interrupt is serviced. t able 122: (tcon) t imer 0, t imer 1 t imer /c ounter control - sfr 88 h 7 6 5 4 tf1 tr1 tf0 tr0 3 2 1 0 ie1 it1 ie0 it0 bit mnemonic function 7 tf1 timer 1 overflow flag set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. 6 tr1 timer 1 run control bit. if cleared timer 1 stops. 5 tf0 timer 0 overflows flag set by hardware when timer 0 ove rflows. this flag can be cleared by software and is automatically cleared when interrupt is processed. 4 tr0 timer 0 run control bit. if cleared timer 0 stops. 3 ie1 interrupt 1 edge flag. set by hardware when falling edge on external int1 is observed. cleared when interrupt is processed. 2 it1 interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. 1 ie0 interrupt 0 edge flag. set by hardware when falling edge on external pin int0 is observed. cleared when inte rrupt is processed. 0 it0 interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. int0 example the following provides example code for interrupt setup and module configuration . // ----------------------------- ---------------------------------------------- // sample c code to setup int0 // --------------------------------------------------------------------------- #pragma tiny #include at 0x0100 void main (void) { // int0 config tcon |= 0x01; //i nterrupt on int0 will be caused by a high - >low //edge on the pin // enable int0 interrupts ien0 |= 0x80; // enable all interrupts ien0 |= 0x01; // enable interrupt int0 // wait for int0? do { }while(1); //wait for int0 interrupts }//end of main f unction // --------------------------------------------------------------------------- // interrupt function void int_ext_0 (void) interrupt 0 { ien0 &= 0x7f; // disable all interrupts /* put the interrupt code here*/ ien0 |= 0x80; // enable all inte rrupts } // --------------------------------------------------------------------------- int1 example the following code example shows the int1 interrupt setup and module configuration: // -------------------------------------------------------------------- ----- // sample c code to setup int1 // ------------------------------------------------------------------------- #pragma tiny #include at 0x0100 void main (void) { // int1 config tcon |= 0x04; //interrupt on int1 will be caused by a high - > low //edge on the pin // enable int1 interrupts ien0 |= 0x80; // enable all interrupts ien0 |= 0x04; // enable interrupt int1 // wait for int1? do { }while(1); //wait for int1 interrupts // interrupt function void int_ext_1 (void) interru pt 2 { ien0 &= 0x7f; // disable all interrupts /* put the interrupt code here*/ ien0 |= 0x80; // enable all interrupts }
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 71 of 80 uart0 and uart1 interrupt example the following program examples demonstrate how to initialization the uart0 and uart1 interru pts. // ------------------------------------------------------------------------------- // sample c code for uart0 and uart1 interrupt example // ------------------------------------------------------------------------------- #pragma tiny #include // --- function prototypes void txmit0( unsigned char charact); void txmit1( unsigned char charact); void uart1config(void); void uart0ws0relcfg(void); // - constants definition sbit uart_tx_empty = userflags^1; // ---------------------------------- ----------------------------------------- // main function // --------------------------------------------------------------------------- at 0x0100 void main (void) { // enable and configure the uart0 & uart1 uart0ws0r elcfg(); //configure uart0 uart1config(); //configure uart1 //*** configure the interrupts ien0 |= 0x91; //enable uart0 int + enable all int ien2 |= 0x01; //enable uart1 interrupt do { }while(1); //wait for uarts interrupts // end of ma in()... // --------------------------------------------------------------------------- // interrupt routines // --------------------------------------------------------------------------- // --------------------------- ------------------------------------------------ // uart0 interrupt // // retrieve character received in s0buf and transmit it // back on uart0 // // ------------------------------------------------------------------------- void int_uart0 (void) interrupt 4 { ien0 &= 0x7f; //disable all interrupts // --- the only uart0 interrupt source is rx... txmit0(s0buf); // return the character //received on uart0 s0con = s0con & 0xfc; //clear r0i & t0i bits ien0 |= 0x80; // enable all interrupts }// end o f uart0 interrupt // --------------------------------------------------------------------------- // uart1 interrupt // // retrieve character received in s1buf and transmit it // back on uart1 // // ---------------------------------------------------------- ----------------- void int_uart1 (void) interrupt 16 { ien0 &= 0x7f; //disable all interrupts // --- the only uart1 interrupt source is rx... txmit1(s1buf); // return the character // received on uart1 s1con = s1con & 0xfc; // clear both r1i & t 1i bits ien0 |= 0x80; // enable all interrupts }// end of uart1 interrupt note: see uart0 / uart1 section for configuration examples and txmitx functions interrupt on p1 c hange the vmx51c1020 includes an interrupt on port change feature, which is a vailable on the port1 pins of the vmx51c1020 . this feature is like having eight extra external interrupt inputs sharing the adc interrupt vector at address 006b h and can be very useful for applications such as switch es, keypads, etc . to activate this i nterrupt, the bit s corresponding to the pins being monitored must be set in the portirqen register . t he adcpcie bit in the ien1 register must be set as well as the ea bit of the ien0 register. t able 123: (portirqen) p ort c hange irq c on figuration - sfr 9f h 7 6 5 4 p17ien p16ien p15ien p4ien 3 2 1 0 p13ien p12ien p11ien p10ien bit mnemonic function 7 p17ien port 1.7 irq on change enable 0 = disable 1 = enable 6 p16ien port 1.6 irq on change enable 0 = disable 1 = enable 5 p15ien port 1.5 irq on change enable 0 = disable 1 = enable 4 p14ien port 1.4 irq on change enable 0 = disable 1 = enable 3 p13ien port 1.3 irq on change enable 0 = disable 1 = enable 2 p12ien port 1.2 irq on change enable 0 = disable 1 = enable 1 p11ien port 1.1 irq on change enable 0 = disable 1 = enable 0 p10ien port 1.0 irq on change enable 0 = disable 1 = enable the portirqstat register monitors the occurrence of the interrupt on port change. this register serves to define which p1 pin has changed wh en an interrupt occurs.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 72 of 80 t able 124: (portirqstat) p ort c hange i rq s tatus - sfr a1 h 7 6 5 4 p17istat p16istat p15istat p14istat 3 2 1 0 p13istat p12istat p11istat p10istat bit mnemonic function 7 p17istat port 1.7 changed 0 = no 1 = yes 6 p16istat port 1.6 changed 0 = no 1 = yes 5 p15istat port 1.5 changed 0 = no 1 = yes 4 p14istat port 1.4 changed 0 = no 1 = yes 3 p13istat port 1.3 changed 0 = no 1 = yes 2 p12istat port 1.2 changed 0 = no 1 = yes 1 p11istat port 1.1 changed 0 = no 1 = yes 0 p10istat port 1.0 changed 0 = no 1 = yes f igure 44: a pplication example o f p ort change interrupt 1 2 3 4 5 6 7 8 9 * 0 # vmx 51 c 1020 p 1 . 4 p 1 . 5 p 1 . 6 p 1 . 7 p 1 . 3 p 1 . 2 p 1 . 1 numeric keypad the following provides an assembler example for configuration of the interrupt on port1 pin change and how it is shar e d with the adc interrupt. include vmixreg.inc ;*** interrupt vectors jump table * org 0000h ;boot origin vector ljmp start org 006bh ;int adc and p1 change interrupt ljmp int_adc_p1 ;*** main program org 0100h start: mov digpwren ,#01h ;enable timer 2 mov p2pincfg,#0ffh ;*** initialise port change interrupt on p1.0 - p1.7 mov portirqstat,#00h mov portirqen,#11111111b ;*** initialise the adc, bgap, pga operation mov analogpwren,#07h ;select ch0 as adc input + enable input buffer + adc clk mov inmuxctrl,#0fh mov adcclkdiv,#0fh mov adcconvrlow,#000h ;*** configure adc conversion rate mov adcconvrmed,#080h mov adcconvrhigh,#016h mov adcctrl,#11111010b ;***activate all interrupts + (serial port for debugger s upport) mov ien0,#090h ;*** enable adc interrupt mov ien1,#020h ;***wait irq? waitirq: ljmp waitirq org 0200h ;************************************************************************ ;* irq routine: irqadc + p1change ;*************** ********************************************************* int_adc_p1: ;mov ien0,#00h ;disable all interrupt ;***check if irq was caused by port change ;***if portirqstat = 00h - > irq comes from adc mov a,portirqstat jz case_adc ;*** if inter rupt was caused by port 1, change case_p0chg: mov portirqstat,#00h ;*** perform other instructions related to port1 change irq ;(...) ;*** jump to interrupt end ajmp endadcp1int ;*** if interrupt was caused by adc case_adc: anl adcctrl,#11110011b ;***reset adc interrupt flags & reset adc for next acquisition orl adcctrl,#080h orl adcctrl,#11111010b ;*** perform other instructions related to port1 change irq ;(...) ;** end of adc and port 1 change interrupt endadcp0int: anl ircon,#11011 111b ;***enable all interrupts before exiting ; mov ien0,#080h reti end
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 73 of 80 the clock control circuit the vmx51c1020 ?s clock control circuit allows dynamic adjust ment of the clock from which the processor and the peripherals derive the ir clock source. this allows reduc tion of overall power consumption by modulating the operating frequency according to processing requirements or peripheral use. a typical application for this can be portable acquisition systems in which significant powe r saving s can be achieved by lowering the operating frequency between a/d conversions and automatically throttling it back to full speed when a n a/d interrupt is generated . note that a/d converter operation is not affected by the clock control unit. the clock control circuit allows adjusting the system clock from [fosc/1] (full speed) down to [fosc/512]. the clock division control is done via the clkdivctrl register located at address 94h of the sfr register area. t able 125: (clkdivct rl) c lock d ivision c ontrol r egister - sfr 94 h 7 6 5 4 softrst - - irqnormspd 3 2 1 0 mckdiv [3:0] bit mnemonic function 7 softrst writing 1 into this bit location provokes a reset. read as a 0 6:5 - - 4 irqnormspd 0 = full speed in irq 1 = selected speed during irqs 3:0 mckdiv [3:0] master clock divisor 0000 ? sys clk 0001 = sys /2 0010 = sys /4 0011 = sys /8 0100 = sys /16 0101 = sys /32 0110 = sys /64 0111 = sys /128 1000 = sys /256 1001 = sys /512 (?) 1111 = sys /512 the value written into the lower nibble of the clkdivctrl register, mckdiv[3:0] , defines the clock division ratio. when the irqnormspd bit is cleared , the vmx51c1020 will run at the maximum operating speed when an interrupt occurs (see following figure ). f igure 45: c lock t iming w hen an i nterrupt o ccurs internal clock interrupt interrupt cleared interrupt set once the interrupt is cleared, the vmx51c1020 returns to the selected operating speed as defined by the mckdiv [3:0] bits of the clkdivctrl register. when the irqnormspd bit is set , the vmx51c1020 w ill continue to operate at the selected speed as defined by the mckdiv [3:0] bits of the clkdivctrl register. note : with the exception of the a/d converter and analog only peripherals such as the current source, potentiometers and op - amp, all the periphe ral operating speed s are affected by the clock control circuit software reset software reset can be generated by setting the softrst bit of the clkdivctrl register to 1 .
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 74 of 80 power - on/brown - out reset the vmx51c1020 includes a power - on - reset/brown - out det ector circuit that ensures the vmx51c1020 enters and stays in the r eset state as long as the supply voltage is below the reset threshold voltage ( order of 3.7 ? 4.0 volts ). in most applications, the vmx51c1020 requires no external components to perform a power - on reset when the device is powered on. the vmx51c1020 includes a reset input for applications in which external reset control is required. the reset pin includes an internal pull - up resistor. when a power - o n reset occurs , all sfr locations return to their default values and peripherals are disabled. errata note: the vmx51c1020 may fail to exit the reset state if the supply voltage drops below the reset threshold, but not below 3v. for applications where this condition can occur, use an externa l supply monitoring circuit to reset the device. processor power control the processor power management unit has two modes of operation: idle and stop mode. idle mode when the vmx51c1020 is in idle mode, the processor clock is halted . however , the inte rnal clock and peripherals continue to run. the power consumption drops because the cpu is not active. as soon as an interrupt or reset occurs, the cpu exits the idle mode . in order to enter idle mode, the user must set the idle bit of the pcon register . any enabled interrupts will force the processor to exit idle mode stop mode in this mode, in contrast to idle mode, all internal clocking shuts down. in order to enter stop mode, the user must set the stop bit of the pcon register. the cpu will ex it this state only when a no n - clocked external interrupt or reset occurs (internal interrupts are not possible because they require clocking activity). the following interrupts can restart the processor from stop mode: reset, int0, int1, spi rx/rx overru n, and the i 2 c interface. f igure 46: p ower m anagement on the vmx51c1020 clkcpu gate clkper gate idle stop interrupt request clk clk for cpu clk for peripherals the following table describes the power control register of the vmx51c1020 . t able 126: (pcon) p ower c ontrol (cpu) - sfr 87 h 7 6 5 4 3 2 1 0 smod - - - gf1 gf0 stop idle bit mnemonic function 7 smod the speed in mode 2 of serial port 0 is controlled by this bit. when smod= 1, f clk /32. this bit is also significant in mode 1 and 3, as it adds a factor of 2 to the baud rate. 6 - - 5 - - 4 - - 3 gf1 not used for power management 2 gf0 not used for power management 1 stop stop mode control bit. setting this bit turns on the stop mode. stop bit is always read as 0. 0 idle idle mode control bit. setting this bit turns on the idle m ode. idle bit is always read as 0.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 75 of 80 watchdog timer the vmx51c1020 ?s watchdog timer is used to monitor p rogram operation and reset the processor in the case where the program code would not be able to refresh the watchdog before it s timeout period has lap sed. this can come about from an event that results in the program counter executing faulty or incorrect code and inhibiting the device from doing its intended job. the watchdog timer consists of a 15 - bit counter composed of two registers ( wdtl and wdth ) and a reload register ( wdtrel ). see following figure. f igure 47: w atch d og t imer 16 2 0 7 control logic 0 7 8 14 wdtrel wdth wdtl wdtr sysclk 12 wdtr wdts (start) (refresh) the wdtl and wdth registers are not accessible from the sfr register. however the wdtrel register makes it possible to load the upper 6 bit s of the wdth register. the pres bit of the wdtrel register selects the clock prescaler that is fed into the watchdog timer. when pres = 0, the clock prescaler = 24 when pres = 1, the clock prescaler = 384 t able 127: (wdtrel) w atch dog t imer r eload r egister - sfr d9 h 7 6 5 4 3 2 1 0 pres wdtrel [6:0] bit mnemonic function 7 pres pre - scaler select bit. when set, the watchdog is clocked through an additional divide - by - 16 pre - scaler. 6 - 0 wdtrel 7 - bit reload value for the high - byt e of the watchdog timer. this value is loaded into the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt. t able 128: (ip0) i nterrupt p riority r egister 0 - sfr b8 h 7 6 5 4 3 2 1 0 uf8 wdtstat ip0 [5:0] bi t mnemonic function 7 uf8 user flag bit 6 wdtstat watchdog timer status flag. set to 1 by hardware when the watchdog timer overflows. must be cleared manually 5 ip0.5 timer 2 port1 change adc 4 ip0.4 uart0 - mult/accu 3 ip0.3 timer 1 - i2c 2 ip0. 2 external int1 - spi rx availlable 1 ip0.1 timer 0 interrupt - spi tx empty 0 ip0.0 external int0 uart1 external int 0 the wdtstat bit of the ip0 register is the watchdog status flag . this bit is set to 1 by the hardware whenever a watchdog timer overflow occurs. this bit must be cleared manually. setting - up the watchdog timer c ontrol of the watchdog timer ?s is enabled by the following bit s: bit location role wdogen digpwren.6 watchdog timer enable wdtr ien0.6 watchdog timer refresh flag wdt s ien1.6 watchdog timer start bit in order for the watchdog to begin counting, the user must set the wdogen bit (bit 6) of digpwren register, as follows: mov digpwren,#x1xxxxxxb ;x=0 or 1 depending ;of other peripherals ;to enable
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 76 of 80 the value written into the wdtrel register defines the delay time of the watchdog timer as follows : wdt delay when the wdtrel bit 7 is cleared wdt delay = 24*[ 32768 ? (wdtrel(6:0) x 256)] fosc wdt delay when the wdtrel bit 7 is set wdt delay = 384 *[ 32768 ? (wdtrel(6:0) x 256)] fosc the following table provides wdt reload va lues and their corresponding delay times fosc wdtrel wdt delay 14.74mhz 00h 53.3ms 14.74mhz 4fh 20.4ms 14.74mhz cch 347ms note: the value present in the clkdivctrl register affect s the watchdog timer delay time. the above equations and examples assu me that the clkdivctrl register content is 00h starting the watchdog timer to start the watchdog timer using the hardware automatic start procedure, the wdts (ien1) and wdtr (ien0) bit s must be set. the watchdog will begin to run with default setting s, i .e. all registers will be set to zero. ;*** do a watchdog timer refresh / start sequence setb ien0.6 ;set the wdtr bit first setb ien1.6 ;then without delay set the ;wdts bit when the wdt registers enter the state 7fffh, the asynchronous signa l, wdts will become active. this signal will set bit 6 in the ip0 register and trigger a reset. to prevent the watchdog timer from resetting the vmx51c1020 , you must reset it periodically by clearing the wdtr and, immediately after wards, clear the wdts bi t. as a security feature to prevent inadvertent clearing of the watchdog timer, no delay (instruction) is allowed between the clearing of the wdtr and the wdts bit s . a) watchdog timer refresh example 1: *** the simple way *** mov ien0,#x1xxxxxxb ;di rect write that set bit ;wdtr (x = 0 or 1) mov ien1,#x1xxxxxxb ;direct write that set bit ;wdts (x = 0 or 1) in the case where the program makes use of the interrupts, it is recommended to deactivate interrupt s before the watch dog refresh is performed and reactivate them after wards . b) watch dog timer refresh example 2: *** if interrupts are used: *** clr ien0.7 ;deactivate the interrupt mov a,ien0 ;retrieve ien0 content orl a,#01000000b ;set the bit 6 (wdtr) xch a,r1 ;store ieno new value mov a, ien1 ;retrieve ien1 content orl a,#01000000b ;set bit 6, (wdts) mov ien0,r1 ; set wdtr bit mov ien1,a ;set wdts bit setb ien0.7 ;reactivate the interrupts watchdog timer reset to de termine whether the reset condition was caused by the watchdog timer , the state of the wdtstat bit of the ip0 register should be monitored . on a standard power on reset condition, this bit is cleared.
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 77 of 80 wdt initialization and use example program org 0000h ;reset & wd irq vector ljmp start ;**************************** ********* ;* main program beginning * ;************************************* org 0100h ;*** initialize wdt and other peripherals*** mov digpwren,#40h ;enable wdt operation ;*** initialize watchdog timer reload value mov wdtrel,#04fh ;the wdtrel re gister is used to ;define the delay time wdt. ;bit 7 of wdtrel define clock ;prescalng value ;bit 6:0 of wdtrel defines the ;upper 7 bits reload value of the ;watchdog timer 15 - bit timer ;*** perform a wdt refresh/start sequence setb ien0.6 ;set the wdtr bit first setb ien1.6 ;then without delay (instruction) ;set the wdts bit right after. ;no delays are permitted between ;setting of the wdtr bit and ;setting of the wdts bit. ;this is a security feature to ;prevent inadvertent rese t/start of ;the wdt ;if other interrupt are enabled, ;it is recommended to disable ;interrupts before refreshing the ;wdt and reactivate them after ;*** wait wdt interrupt waitwdt: nop ;*** if the two following code lines below are put "in - comment", the ;***wdt will trigger a reset, and the program will restart. ;*** perform a watchdog timer refresh/start sequence ;setb ien0.6 ;set the wdtr bit first ;setb ien1.6 ;then without delay (instruction) ljmp waitwdt ;set the wdts bit right after. ;no delays are permitted between ;setting of the wdtr bit and ;setting of wdts bit. ;this is a security feature to ;prevent inadvertent reset/start of ;the wdt ;it is recommended to disable ;interrupts before refreshing the ;wdt and reactivate them after vmx51c1020 programming when the pm pin is set to 1, the i2c interface becomes the programming interface for the vmx51c1020 ?s flash memory. an i n - circuit programming interface is easy to implement at the board level. see vmix app - n ote001. erasing and programming the vmx51c1020 ?s flash memory requires an external programming voltage of 12v. this programming voltage is supplied /controlled by the programming hardware/tools . the vmx51c1020 can be programmed using the ramtron in - circui t programmer . f igure 48: vmx51c1020 p rogramming versa - icp target pc board r s - 2 3 2 5 v ( optional ) scl sda vpp 12 v pm res - ( reset ) gnd
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 78 of 80 vmx51c1020 debugger the vmx51c1020 includes hardware debugging features that speed - up embedded software development time . debugger features the vmx51c1020 debugger supports b reakpoints and single - stepping of the user program. it supports re triev al and edit ing of the content s of the sfr registers and ram memory contents when a breakpoint is reached or when the device operates in single - step mode. unlike rom monitor programs t hat execute user program instruction at a much lower speed, the vmx51c1020 debugger does not affect program operating speed when in ?run mode? before encountering a breakpoint . debugger hardware interface t he vmx51c1020 ?s development system provides the ideal platform for run ning the debugger . interfacing to the vmx51c1020?s debugger is done via the uart0 serial interface. it is possible to run the vmx51c1020 debugger on the end user pcb provided that access to the vmx51c1020 ?s uart0 is available . howe ver , a connection to a stand a lone in - circuit programmer (icp) will be required to perform flash programming, control of the reset line , and to activate the debugger on the target vmx51c1020 device. f igure 49: vmx51c1020 d ebugger h ardware interface versa - icp target pc board to uart 0 rs 232 transceiver versa ware vmx software r s - 2 3 2 r s - 2 3 2 debugger software interface the versa ware vmx51c1020 / versa1 windows ? software provides an easy to use user interface for in - circuit debugging for more details on the vmx51c1020 debugger , see the ? versa ware vmx51c1020 - v1 software user guide.pdf? all documents are accessible on the ramtron inc. website at www.ramtron.com
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 79 of 80 vmx51c1020 64 pin quad flat package 0 . 20 rad . typ . b 0 . 17 max l 6 4 0 . 30 rad . typ . 0 . 25 a 10 10 a 2 a 1 e a 1 package thickness 2 . 00 body + 3 . 20 mm footprint dims . a max . a 1 +. 10 / - . 05 a 2 . 25 d . 10 d 1 . 25 e e 1 . 10 l +. 15 / - . 10 e basic b . 05 tols . leads 64 l 2 . 35 17 . 20 14 . 00 17 . 20 2 . 00 0 . 25 max . 80 . 88 14 . 00 0 o - 7 o . 35 notes : 1 ) all dimensions are in millimeters 2 ) dimensions shown are nominal with tolerances as indicated . 3 ) foot length " l " is measured at gage plane , 0 . 25 above seating plane standoff seating plane d 1 d e 1 e 64 vmx 51 c 1020 qfp - 64 a 1
vmx51c1020 _________________________________________________________________________________________________ www.ramtron.com page 80 of 80 ordering information device number structure vmx51c1020 ordering options device number package option operati ng voltage temperature frequency vmx51c1020 - 14 - q c qfp - 64 4.75v to 5.5v 0c to +70c 14.75mhz vmx51c1020 - 14 - qc g qfp - 64 4.75v to 5.5v 0c to +70c 14.75mhz *see errata information below vmx51c1020 errata the vmx51c1020 operating frequency and temperatur e range have been revised with more conservative values. the maximum operating frequency specifications of the vmx51c1020 has been revised to 14.75mhz and its operating temperature range to 0oc to 70oc. these new specifications affect all the vmx51c1020 d evices with the markings of vmx51c1020 - qai16. in order to reflect the specification updates of the vmx51c1020 , the new vmx51c1020 devices that have the same silicon version, features and performances as the vmx51c1020 - qai16 will now be marked vmx51c1020 - qa c14. disclaimer right to make changes - ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. customers should obtain the most current and relevant information before placing orders. use in applications - ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties tha t these products are free from patent, copyright or mask work right infringement unless otherwise specified. customers are responsible for product design and applications using ramtron parts. ramtron assumes no liability for applications assistance or cust omer product design. life support ? ramtron products are not designed for use in life support systems or devices. ramtron customers using or selling ramtron products for use in such applications do so at their own risk and agree to fully indemnify ramtron for any damages resulting from such applications. note: pc is a registered trademark of ibm corp. windows is a registered trademark of microsoft corp. i2c is a registered trademark of philips corporation. spi is a registered trademark of motorola inc. a ll other trademarks are the property of their respective owners.

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